I wrote:
> The problem here is that CPU#1 fails to hold clock_lock while setting
> clkintr_pending, causing i8254_offset to be stepped twice, first due
> to clkintr_pending, then due to i8254_lastcount being larger than count.
With this patch applied to RELENG_4, the clock speedup seems to disappear.
--- apic_vector.s.old Fri Mar 2 13:47:31 2001
+++ apic_vector.s Fri Aug 31 01:07:53 2001
@@ -707,7 +707,12 @@
FAST_INTR(21,fastintr21)
FAST_INTR(22,fastintr22)
FAST_INTR(23,fastintr23)
-#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
+#define CLKINTR_PENDING pushl $clock_lock; \
+ call s_lock; \
+ movl $1,CNAME(clkintr_pending); \
+ call s_unlock; \
+ addl $4, %esp
+
INTR(0,intr0, CLKINTR_PENDING)
INTR(1,intr1,)
INTR(2,intr2,)
The corresponding patch for -current is
Index: apic_vector.s
===================================================================
RCS file: /home/ncvs/src/sys/i386/isa/apic_vector.s,v
retrieving revision 1.71
diff -u -r1.71 apic_vector.s
--- apic_vector.s 27 Apr 2001 19:28:21 -0000 1.71
+++ apic_vector.s 31 Aug 2001 01:35:05 -0000
@@ -7,6 +7,8 @@
#include <machine/apic.h>
#include <machine/smp.h>
+#include <machine/mutex.h>
+
#include "i386/isa/intr_machdep.h"
/* convert an absolute IRQ# into a bitmask */
@@ -384,7 +425,11 @@
FAST_INTR(29,fastintr29)
FAST_INTR(30,fastintr30)
FAST_INTR(31,fastintr31)
-#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
+#define CLKINTR_PENDING MTX_LOCK_SPIN(clock_lock, 0); \
+ movl $1,CNAME(clkintr_pending); \
+ MTX_UNLOCK_SPIN(clock_lock)
+
+
/* Threaded interrupts */
INTR(0,intr0, CLKINTR_PENDING)
INTR(1,intr1,)
- Tor Egge
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