A number of new chips have been released lately, along with some
enhancements to existing processors that all fall into the same
logic of parallelizing some operations. Why, just today I ran
across an article about http://www.theregister.co.uk/content/3/20576.html,
which bosts 128 ALU's on a single chip.
This got me to thinking about an interesting way of using these
chips. Rather than letting the hardware parallelize instructions
from a single stream, what about feeding it multiple streams of
instructions. That is, treat it like multiple CPU's running two
(or more) processes at once.
I'm sure the hardware isn't quite designed for this at the moment
and so it couldn't "just be done", but if you had say 128 ALU's
most single user systems could dedicate one ALU to a process
and never context switch, in the traditional sense. For systems
that run lots of processors the rate limiting on a single process
wouldn't be a big issue, and you could gain lots of effiencies
in the global aspect by not context-switching in the traditional
sense.
Does anyone know of something like this being tried? Traditional
2-8 way SMP systems probably don't have enough processors (I'm
thinking 64 is a minimum to make this interesting) and require
other glue to make multiple independant processors work together.
Has anyone tried this with them all in one package, all clocked
together, etc?
--
Leo Bicknell - [EMAIL PROTECTED]
Systems Engineer - Internetworking Engineer - CCIE 3440
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