On Mon, 16 Jul 2001, Bill Paul wrote:
> > On Mon, 16 Jul 2001, Bill Paul wrote:
> >
> > > They're "okay." The NatSemi chip has one flaw, which is that RX buffers
> > > must be aligned on a 64-bit boundary. None of the more expensive NICs have
> > > this restriction.
> >
> > Go ahead and beat me up if you have to :-) But why is there _any_ issue
> > with RX buffer alignment? I get some mbufs and set the data pointer to
> > any point I want, or I get a cluster, which is always on a 2k boundary.
>
> The OS wants the _payload_ to be aligned on a 32-bit boundary. It tries
> to do 32-bit accesses to the IP header, and the NFS code also does 32-bit
> accesses when trying to un-XDR NFS requests.
Oh... I see... I guess you could grab an mbuf and copy just the IP
header for that, no? (Just curious at this point :-)
> But on other CPUs such as the alpha, SPARC, PPC and (I suspect) the
> IA-64, unaligned accesses in the kernel generate a fatal trap and a
> panic. In user space, an unaligned access may result in a bus error,
> unless the OS is kind enough to handle the trap, which I believe
> FreeBSD/alpha does.
I don't think that is the case. I seem to remember FreeBSD Alpha 4.3
sysinstall croaking on me once with an alignment error.
> Most chips place no restrictions on the alignment of TX buffers. The only
> exceptions I know of where the chip API simply doesn't permit it are the
> RealTek 8139/if_rl (surprise) and the VIA Rhine I and Rhine II/if_vr.
And the IDT 77211 ATM SAR chip. Fortunately, most of the PDUs I see
are perfectly aligned, and no copy is needed.
Thanks for the explanation!
-Richard
-------------------------------------------
Richard Hodges | Matriplex, inc.
Product Manager | 769 Basque Way
[EMAIL PROTECTED] | Carson City, NV 89706
775-886-6477 | www.matriplex.com
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