On 2001-07-10, Josh M Osborne scribbled:
# The current Intel's have a shared bus, and all memory traffic goes
# over it, and some cache coherency traffic as well.
The official names of Intel's bus include: GTL, GTL+, AGTL and AGTL+.
The new iTanic (aka Itanium) processor uses the AGTL+ protocol whereas
the Pentium II/III use the GTL protocol. The Pentium 4 uses the GTL+
which allows for the quad-pumped 100Mhz FSB. I could have mixed up which
processor uses which... but you get the idea :)
# The AMD's/EV6's have a memory bus PER CPU plus a coherency bus.
# I think the coherency bus may even be point-to-point between the
# CPU and coherency controller, not a all the CPUs with the coherency
# controller being responsible for routing messages as needed.
If I read the specs correctly on the EV6 protocol... each CPU has a
separate connection to the 'northbridge' chip. It's up to the
northbridge to provide connectivity to the memory.
# It is clearly a more expensive, more complex system. It also allows
# much higher memory bandwidth (if two CPUs are looking at different
# chunks of the address space they get their own path to memory). If
# the coherency "bus" really is point-to-point the coherency controller
# has to have a big chunk of SRAM, but you should be able to get
# dramatically more CPUs to access memory quickly.
The biggest problem is the number of traces required... which is more
than double of that found in a single-processor configuration. Also,
there is a memory bandwidth bottleneck if you have both processors
hitting memory... there isn't a lot of bandwidth left open for other
devices ;-)
# That may explain why you can buy Alpha systems with 40+ CPUs, and
# Intel XENON boxes with no more then eight (or is it four?). It is
# also part of why the big Alphas are costly, but only part of it...
32-way machines are built differently than your 2-way or 4-way servers.
Some use cellular multi-processing, some use NUMA, and many other
techologies and concepts to allow massive number of processors within a
single server. You can build a 32-way Xeon machine (Unisys has...
NUMA-Q... which used to be Sequent, I believe has a 32-way configuration
available) but they are very, very expensive... mostly when each 'pod'
or 'cell' requires 2+ Meg of coherency cache... plus the numerous
amounts of memory channels.
--
Linh Pham
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