Aloha!
In an earlier mail to the thread I pointed to the STREAM benchmark for
memory sub systems. Additionally, I wrote that I knew there were another
benchmark that tries to analyze word sizes, access latencies for the
different memories in the mem sub system. I know can name that benchmark
(or at least one such benchmark): MOB. Check out:
http://steamboat.cs.ucsb.edu/mob/
The benchmark is currently not in the ports, but it has been tested (see
the mob home page) on FreeBSD. I have downloaded it, compiled it and are
measuring my own system while writing this. [1]
Additionally, the following page is a pretty comprehensive list of links
to tools and documentation relating to performance measurement, analysis
and optimization.
http://www.cs.virginia.edu/~clc5q/perflinks.html
[1] MOB reported the following for my Dual Celeron 533 system:
Allocated 64MB of memory for benchmarking
Performing benchmark: Cache Size/Levels
Data Caches:
Found L1: [16384]
Found L2: [131072]
Found L3: [8388608]
Instruction Caches:
Found L1: [16384]
Found L2: [131072]
Performing benchmark: Cache Share
Level 1 cache is not shared
Level 2 cache is shared
Performing benchmark: Cache Line Size
Data Caches:
Elected line size: 32
Elected line size: 28
Elected line size: 108
Instruction Caches:
Elected line size: 100
Performing benchmark: Cache Associativity
Data Caches:
Detected L1 is 8-way associative.
Detected L2 is 4-way associative.
Detected L3 is 4-way associative.
Instruction Caches:
Detected L1 is 4-way associative.
Performing benchmark: Cache Replacement Policy
Data Caches:
Detected L1 is random replacement policy
Detected L2 is random replacement policy
Detected L3 is random replacement policy
Instruction Caches:
Detected L1 has LRU replacement policy
Performing benchmark: Cache Write Policy
Data Caches:
Found L1 replacement policy is write-back/allocate
Found L2 replacement policy is write-back/allocate
Found L3 replacement policy is write-through/no-allocate
Performing benchmark: Cache Indexing (Virtual/Physical)
Performing benchmark: TLB Page Size
Data TLBs:
Instruction TLBs:
Performing benchmark: TLB Entry Count
Data TLBs:
Num entries: 10
Instruction TLBs:
Number of entries not detected
Performing benchmark: TLB Associativity
Data TLBs:
Found associativity 32
Instruction TLBs:
Found associativity 32
# MOB Config file
# Date Fri Mar 16 17:50:35 2001
# Host: fetis.ninja.se
# Run params: trials=3 runTime=1000000 verbosity=2
[CACHE]
level = 1
type = Data
size = 16384
lineSize = 32
associativity = 8
replacement = random
writeMode = writeBack-alloc
latency =
[CACHE]
level = 2
type = Shared
size = 131072
lineSize = 28
associativity = 4
replacement = random
writeMode = writeBack-alloc
latency = 1.0869
[CACHE]
level = 3
type = Data
size = 8388608
lineSize = 108
associativity = 4
replacement = random
writeMode = writeThrough-noalloc
latency = 235.7955
[CACHE]
level = 1
type = Instruction
size = 16384
lineSize = 100
associativity = 4
replacement = lru
writeMode =
latency = 1.0397
[TLB]
type = Data
pageSize = 524288
numEntries = 10
associativity = 32
latency =
[TLB]
type = Instruction
pageSize = 1024
numEntries =
associativity = 32
latency =
--
Cheers!
Joachim - Alltid i harmonisk svängning
--- FairLight ------ FairLight ------ FairLight ------ FairLight ---
Joachim Strömbergson ASIC SoC designer, nice to CUTE animals
Phone: +46(0)31 - 27 98 47 Web: http://www.ludd.luth.se/~watchman
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