On Friday 03 June 2011 02:03 am, Andriy Gapon wrote: > on 01/06/2011 23:55 Jung-uk Kim said the following: > > Yes, it's still a work-in-progress. However, I thought it is > > good enough for 9.0 inclusion. BTW, the latest patch is here: > > > > http://people.freebsd.org/~jkim/tsc_smp_test5.diff > > > > FYI, the only meaningful change from the previous version is that > > it's limited to AMD single-socket Bulldozer platforms and Intel > > Core and later platforms. We may add more quirks if needed, of > > course. > > Looks good, but I think that the check is a little bit unfair to > AMD Family 10h+ CPUs. Although TSCs in those CPUs are per core > I've never seen them drift out of sync if they started with the > same value.
[snip] Unlike Intel, AMD did not guarantee "all TSCs reset to zero with RESET IPI" before Bulldozer[1]. In fact, I tried to measure deltas between cores when I started hacking on it using some crude heuristics, somewhat like the OpenSolaris hack[2]. Basically, a dual-core AMD Family 10h processor showed noticeably larger deltas than *two* dual-core Intel Woodcrest Xeons'. Jung-uk Kim [1] I couldn't find any clues from their publicly available documents whether they will implement (or need) additional mechanism for multi-socket Bulldozer platforms. It only says something like "all TSCs are synchronized with a clock source in north bridge". We will see when AMD Valencia & Interlagos are available. :-) [2] Unfortunately, there is no way to accurately measure it with current generation hardware. _______________________________________________ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to "freebsd-hackers-unsubscr...@freebsd.org"
