In message <pine.bsf.4.05.9906191302400.16699-100...@medulla.hippocampus.net> Marc Nicholas writes: : Hmmm...I always thought there was something "broke" inside Celerons to : prevent SMP...maybe I'm wrong? Sure would be neat if you could run them : SMP...
What is "broke" about the Celerons is their cache. Without a good cache sharing, you can't get good SMP performance. While you can run a SMP Celeron machine, it won't scale as well as the PII version of the chip. Warner To Unsubscribe: send mail to majord...@freebsd.org with "unsubscribe freebsd-hackers" in the body of the message
