Are there plans to add support for PAT on Intel P6 and AMD Athlon processors?
This feature provides more flexible interface allowing to setup various memory
cache modes on a page-by-page bases. It is much easier to program than MTRRs
and does not suffer from their size/alignment limitations. Provided there
are patches to support PAT in kernel, how it should be exposed to the user
level code? Will something like mmprotect system call suffice?

-Alex


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