On Wed, Nov 28, 2012 at 05:24:35PM +0200, Andriy Gapon wrote: > on 26/11/2012 09:10 Alex Chistyakov said the following: > > CPU: Intel(R) Core(TM) i7-3930K CPU @ 3.20GHz (3200.18-MHz K8-class CPU) > > Origin = "GenuineIntel" Id = 0x206d7 Family = 0x6 Model = 0x2d > > Stepping = 7 > > Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE> > > Features2=0x1fbee3bf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,DCA,SSE4.1,SSE4.2,x2APIC,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,AVX> > > AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM> > > AMD Features2=0x1<LAHF> > > TSC: P-state invariant, performance statistics > > > > Is this a multi-socket system? > > It would be very strange that a modern CPU like this would have such a skew > between TSC on different cores. > > On my Core i5-3570 I see that the _observed_ skew is no more than 100 ticks > (after > many days of uptime). It could be zero, in fact, given the inaccuracy of > inter-core measurements.
I believe that Cores have single TSC per package, located in uncore. And Core i7 cannot work in multi-socket systems.
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