On 04/19/10 02:30, Alexander Motin wrote: > Rui Paulo wrote: >> On 18 Apr 2010, at 14:05, Alexander Motin wrote: >>> Most of AHCI controllers could also work as usual PCI ATA, but not every >>> PCI ATA could work as AHCI. It would be nice to compare `pciconf -lvbc` >>> output in both working (Rui) and not working (Michael) cases. >> >> ah...@pci0:0:31:2: class=0x01018f card=0x72708086 chip=0x27c48086 rev=0x02 >> hdr=0x00 >> vendor = 'Intel Corporation' >> device = '82801GBM/GHM (ICH7-M Family) Serial ATA Storage Controller' >> class = mass storage >> subclass = ATA > > ^^^ > It doesn't report itself as AHCI. > >> bar [10] = type I/O Port, range 32, base 0x20d8, size 8, enabled >> bar [14] = type I/O Port, range 32, base 0x20fc, size 4, enabled >> bar [18] = type I/O Port, range 32, base 0x20d0, size 8, enabled >> bar [1c] = type I/O Port, range 32, base 0x20f8, size 4, enabled >> bar [20] = type I/O Port, range 32, base 0x2020, size 16, enabled >> bar [24] = type Memory, range 32, base 0x90445000, size 1024, enabled > > This resource (BAR(5)) is absent on Michael's system. It is needed to > work in AHCI mode, but not required for legacy PCI ATA. Probably some > kind of BIOS magic in your case makes it appear in this mode with this > chip ID.
More for my own amusement than anything, I came up with an _horrible_
patch to force my ICH7M into AHCI mode (attached). It has two issues:
1) I haven't figured out how to automagically determine which
address(es) I can use without colliding with anything else. Simply
letting bus_allocate_any() decide where to point BAR(5) doesn't appear
to work. I suspect I have to dig through the SMAP stuff to find out what
the BIOS has already claimed and use something outside of those ranges.
2) Since my laptop has both a SATA drive and a PATA DVD-R/W, the
manufacturer commissioned a BIOS which brings the ICH7M up in "combined
mode" with D31-F1 completely disabled. Since it can't (per Intel spec)
be re-enabled without a "platform reset", flipping into AHCI mode
effectively removes the DVD.
However - on the "up side", I now get NCQ ;-)
ahci0: <Intel ICH7M AHCI SATA controller> port
0x1f0-0x1f7,0x3f6,0x170-0x177,0x376,0x18b0-0x18bf
at device 31.2 on pci0
ahci0: BAR(5): 0xf0d44400 AHCI_CAP: 0xdf12ff03 PI: 0x1
pcib0: matched entry for 0.31.INTB
pcib0: slot 31 INTB hardwired to IRQ 19
ahci0: [MPSAFE]
ahci0: [ITHREAD]
ahci0: AHCI v1.10 with 4 1.5Gbps ports, Port Multiplier supported
ahci0: Caps: 64bit NCQ MPS SS ALP AL CLO 1.5Gbps PM PMD SSC PSC
32cmd 4ports
ahci0: Caps2:
ahcich0: <AHCI channel> at channel 0 on ahci0
ahcich0: [MPSAFE]
ahcich0: [ITHREAD]
ahcich0: Caps:
[ .. ]
ada0 at ahcich0 bus 0 scbus1 target 0 lun 0
ada0: <FUJITSU MHZ2320BJ G2 0000001E> ATA-8 SATA 2.x device
ada0: Serial Number K82BT89256VDGEOM: new disk ada0
ada0: 150.000MB/s transfers (SATA 1.x, UDMA5, PIO 8192bytes)
ada0: Command Queueing enabled
ada0: 305245MB (625142448 512 byte sectors: 16H 63S/T 16383C)
*** sys/dev/ahci/ahci.c.orig Sat Apr 24 21:36:42 2010
--- sys/dev/ahci/ahci.c Sun Apr 25 21:30:57 2010
***************
*** 126,131 ****
--- 126,132 ----
{0x26838086, 0x00, "Intel ESB2", 0},
{0x27c18086, 0x00, "Intel ICH7", 0},
{0x27c38086, 0x00, "Intel ICH7", 0},
+ {0x27c48086, 0x00, "Intel ICH7M", 0},
{0x27c58086, 0x00, "Intel ICH7M", 0},
{0x27c68086, 0x00, "Intel ICH7M", 0},
{0x28218086, 0x00, "Intel ICH8", 0},
***************
*** 321,331 ****
--- 322,353 ----
ctlr->quirks = ahci_ids[i].quirks;
resource_int_value(device_get_name(dev),
device_get_unit(dev), "ccc", &ctlr->ccc);
+
+ #define AHCI_MEM_HACK 0xF0D44400 /* 0xf0d443ff is the last used by
others on Toshiba A105 */
+
+ /* Need to set the SCRAE bit and ensure SCRD not set */
+ pci_write_config(dev, 0x94, (pci_read_config(dev, 0x94, 4) | 0x200) &
~0x4000, 4);
+ /* enable MSE */
+ pci_write_config(dev, 0x4, (pci_read_config(dev, 0x4, 2) | 2), 2);
+ pci_write_config(dev, 0x24, AHCI_MEM_HACK, 4);
+ pci_write_config(dev, 0x90, 0x40, 1); /* AHCI + non-combined */
+
+ /* allocate a free memory window for BAR(5) */
+ ctlr->r_rid = PCIR_BAR(5);
+ bus_set_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, AHCI_MEM_HACK,
0x400);
+
/* if we have a memory BAR(5) we are likely on an AHCI part */
ctlr->r_rid = PCIR_BAR(5);
if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&ctlr->r_rid, RF_ACTIVE)))
return ENXIO;
+
+ /* enable ICH7M ports in AHCI space */
+ ATA_OUTL(ctlr->r_mem, AHCI_PI, ATA_INL(ctlr->r_mem, AHCI_PI) | 5);
+ #if 0
+ device_printf(dev, "BAR(5): 0x%lx AHCI_CAP: 0x%lx PI: 0x%lx\n",
(unsigned long)pci_read_config(dev, 0x24, 4),
+ (unsigned long)ATA_INL(ctlr->r_mem, 0), (unsigned
long)ATA_INL(ctlr->r_mem, AHCI_PI));
+ #endif
/* Setup our own memory management for channels. */
ctlr->sc_iomem.rm_type = RMAN_ARRAY;
ctlr->sc_iomem.rm_descr = "I/O memory addresses";
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