Does the following, untested, patch help any better than your gross
kludges? It forces 12 bit aligment of the allocations for CardBus
devices as well as for 'R2' 16-bit devices (which were already
forced). One might be able to share the 4k range between devices if
one had, say, two xl cards (I'd have to look hard at the code to be
sure), but very few machines are so memory constrained as to make that
a big win for the hair it would add to the code.
Warner
Index: pccbb.c
===================================================================
RCS file: /home/ncvs/src/sys/dev/pccbb/pccbb.c,v
retrieving revision 1.78
diff -u -r1.78 pccbb.c
--- pccbb.c 12 Jun 2003 06:06:14 -0000 1.78
+++ pccbb.c 17 Jun 2003 13:18:30 -0000
@@ -1543,6 +1550,9 @@
start = cbb_start_mem;
if (end < start)
end = start;
+ if (RF_ALIGNMENT(flags) < CBB_MEMALIGN_BITS)
+ flags = (flags & ~RF_ALIGNMENT_MASK) |
+ rman_make_alignment_flags(CBB_MEMALIGN);
break;
}
Index: pccbbreg.h
===================================================================
RCS file: /home/ncvs/src/sys/dev/pccbb/pccbbreg.h,v
retrieving revision 1.12
diff -u -r1.12 pccbbreg.h
--- pccbbreg.h 23 Nov 2002 23:09:45 -0000 1.12
+++ pccbbreg.h 17 Jun 2003 13:18:31 -0000
@@ -75,7 +75,9 @@
#define CBBR_IOBASE1 0x34 /* len=4 */
#define CBBR_IOLIMIT1 0x38 /* len=4 */
#define CBB_MEMALIGN 4096
+#define CBB_MEMALIGN_BITS 12
#define CBB_IOALIGN 4
+#define CBB_IOALIGN_BITS 2
#define CBBR_INTRLINE 0x3c /* len=1 */
#define CBBR_INTRPIN 0x3d /* len=1 */
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