:
: critical_enter(); <<<<<<<<<
: *CMAP2 = PG_V | PG_RW | phys | PG_A | PG_M; <<<<<<<<<
: invltlb_1pg((vm_offset_t)CADDR2); <<<<<<<<<
: curthread->td_lazytlb = PCPU_GET(cpumask); <<<<<<<<<
: critical_exit(); <<<<<<<<<
:
:...
:
: Then we mod the scheduler to check td_lazytlb against PCPU_GET(cpumask)
: when it switches a thread in. If the bit is not set it clears the TLB
: and sets the bit.
:
: Now, obviously the above is all just pseudo code. We would want to
: properly abstract the API and fields, but I think it solves the problem
: quite nicely, at least in concept.
:
: -Matt
Another thing we could do is provide a low-level scheduler callback
in the thread. So the lazyzero code would set up a function that
invalidates just the CMAP entry it uses on switch-in:
curthread->td_swcallback = pmap_lazyzero_tlbinval;
void
pmap_lazyzero_tlbinval(void)
{
: invltlb_1pg((vm_offset_t)CADDR2);
}
This is even better then my first idea.
-Matt
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