On Wed, Nov 06, 2013 at 12:30:05PM -0500, John Baldwin wrote: > On Wednesday, November 06, 2013 4:12:24 am Dmitry Luhtionov wrote: > > --- /usr/src/sys/amd64//amd64/identcpu.c.orig 2013-11-01 > > 14:43:15.000000000 +0200 > > +++ /usr/src/sys/amd64//amd64/identcpu.c 2013-11-04 12:06:06.000000000 > > +0200 > > @@ -366,14 +366,14 @@ > > "\017<b14>" > > "\020LWP" /* Lightweight Profiling */ > > "\021FMA4" /* 4-operand FMA instructions */ > > - "\022<b17>" > > + "\022TCE" /* Translation Cache Extension */ > > "\023<b18>" > > "\024NodeId" /* NodeId MSR support */ > > "\025<b20>" > > "\026TBM" /* Trailing Bit Manipulation */ > > "\027Topology" /* Topology Extensions */ > > - "\030<b23>" > > - "\031<b24>" > > + "\030PCXC" /* Core performance counter extensions */ > > + "\031PNXC" /* NB performance counter extensions */ > > "\032<b25>" > > "\033<b26>" > > "\034<b27>" > > It would be best to also add flags for these in specialreg.h as well. The > i386 identcpu.c might also need updating.
There is apparently more bits defined in the BKDG for Kabini.
Below is the patch which I plan to commit shortly.
diff --git a/sys/amd64/amd64/identcpu.c b/sys/amd64/amd64/identcpu.c
index 27ea9a6..3712fc0 100644
--- a/sys/amd64/amd64/identcpu.c
+++ b/sys/amd64/amd64/identcpu.c
@@ -366,18 +366,18 @@ printcpuinfo(void)
"\017<b14>"
"\020LWP" /* Lightweight Profiling */
"\021FMA4" /* 4-operand FMA instructions */
- "\022<b17>"
+ "\022TCE" /* Translation Cache Extension
*/
"\023<b18>"
"\024NodeId" /* NodeId MSR support */
"\025<b20>"
"\026TBM" /* Trailing Bit Manipulation */
"\027Topology" /* Topology Extensions */
- "\030<b23>"
- "\031<b24>"
+ "\030PCXC" /* Core perf count */
+ "\031PNXC" /* NB perf count */
"\032<b25>"
- "\033<b26>"
- "\034<b27>"
- "\035<b28>"
+ "\033DBE" /* Data Breakpoint extension */
+ "\034PTSC" /* Performance TSC */
+ "\035PL2I" /* L2I perf count */
"\036<b29>"
"\037<b30>"
"\040<b31>"
diff --git a/sys/i386/i386/identcpu.c b/sys/i386/i386/identcpu.c
index beec9b1..1af3ac2 100644
--- a/sys/i386/i386/identcpu.c
+++ b/sys/i386/i386/identcpu.c
@@ -842,18 +842,18 @@ printcpuinfo(void)
"\017<b14>"
"\020LWP" /* Lightweight Profiling */
"\021FMA4" /* 4-operand FMA instructions */
- "\022<b17>"
+ "\022TCE" /* Translation Cache Extension
*/
"\023<b18>"
"\024NodeId" /* NodeId MSR support */
"\025<b20>"
"\026TBM" /* Trailing Bit Manipulation */
"\027Topology" /* Topology Extensions */
- "\030<b23>"
- "\031<b24>"
+ "\030PCXC" /* Core perf count */
+ "\031PNXC" /* NB perf count */
"\032<b25>"
- "\033<b26>"
- "\034<b27>"
- "\035<b28>"
+ "\033DBE" /* Data Breakpoint extension */
+ "\034PTSC" /* Performance TSC */
+ "\035PL2I" /* L2I perf count */
"\036<b29>"
"\037<b30>"
"\040<b31>"
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index 4247ee2..3d20e61 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -201,9 +201,15 @@
#define AMDID2_WDT 0x00002000
#define AMDID2_LWP 0x00008000
#define AMDID2_FMA4 0x00010000
+#define AMDID2_TCE 0x00020000
#define AMDID2_NODE_ID 0x00080000
#define AMDID2_TBM 0x00200000
#define AMDID2_TOPOLOGY 0x00400000
+#define AMDID2_PCXC 0x00800000
+#define AMDID2_PNXC 0x01000000
+#define AMDID2_DBE 0x04000000
+#define AMDID2_PTSC 0x08000000
+#define AMDID2_PTSCEL2I 0x10000000
/*
* CPUID instruction 1 eax info
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