--- sys/dev/ata/chipsets/ata-intel.c
+++ sys/dev/ata/chipsets/ata-intel.c
@@ -85,6 +85,18 @@ static void ata_intel_31244_reset(device_t dev);
 #define INTEL_6CH2	8
 #define INTEL_ICH7	16
 
+struct ata_intel_data {
+	u_char		smap[8]; /* was a void* */
+	struct mtx	lock;
+};
+
+#define ATA_INTEL_SMAP(_ctlr, _ch) \
+    &((struct ata_intel_data *)(_ctlr->chipset_data))->smap[_ch->unit * 2]
+#define ATA_INTEL_LOCK(_ctlr) \
+    mtx_lock(&((struct ata_intel_data *)(_ctlr->chipset_data))->lock)
+#define ATA_INTEL_UNLOCK(_ctlr) \
+    mtx_unlock(&((struct ata_intel_data *)(_ctlr->chipset_data))->lock)
+
 /*
  * Intel chipset support functions
  */
@@ -217,7 +229,10 @@ ata_intel_chipinit(device_t dev)
     if (ata_setup_interrupt(dev, ata_generic_intr))
 	return ENXIO;
 
-    ctlr->chipset_data = NULL;
+    struct ata_intel_data *data = malloc(sizeof(struct ata_intel_data),
+        M_DEVBUF, M_WAITOK | M_ZERO);
+    mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF);
+    ctlr->chipset_data = (void *)data;
 
     /* good old PIIX needs special treatment (not implemented) */
     if (ctlr->chip->chipid == ATA_I82371FB) {
@@ -329,7 +344,7 @@ ata_intel_ch_attach(device_t dev)
 
 	ch->flags |= ATA_ALWAYS_DMASTAT;
 	if (ctlr->chip->max_dma >= ATA_SA150) {
-		smap = (u_char *)&ctlr->chipset_data + ch->unit * 2;
+		smap = ATA_INTEL_SMAP(ctlr, ch);
 		map = pci_read_config(device_get_parent(dev), 0x90, 1);
 		if (ctlr->chip->cfg1 & INTEL_ICH5) {
 			map &= 0x07;
@@ -415,7 +430,7 @@ ata_intel_reset(device_t dev)
 		return (ata_generic_reset(dev));
 
 	/* Do hard-reset on respective SATA ports. */
-	smap = (u_char *)&ctlr->chipset_data + ch->unit * 2;
+	smap = ATA_INTEL_SMAP(ctlr, ch);
 	mask = 1 << smap[0];
 	if ((ch->flags & ATA_NO_SLAVE) == 0)
 		mask |= (1 << smap[1]);
@@ -605,7 +620,7 @@ ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result)
 	ctlr = device_get_softc(parent);
 	ch = device_get_softc(dev);
 	port = (port == 1) ? 1 : 0;
-	smap = (u_char *)&ctlr->chipset_data + ch->unit * 2;
+	smap = ATA_INTEL_SMAP(ctlr, ch);
 	offset = 0x100 + smap[port] * 0x80;
 	switch (reg) {
 	case ATA_SSTATUS:
@@ -635,7 +650,7 @@ ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result)
 	parent = device_get_parent(dev);
 	ctlr = device_get_softc(parent);
 	ch = device_get_softc(dev);
-	smap = (u_char *)&ctlr->chipset_data + ch->unit * 2;
+	smap = ATA_INTEL_SMAP(ctlr, ch);
 	port = (port == 1) ? 1 : 0;
 	switch (reg) {
 	case ATA_SSTATUS:
@@ -650,9 +665,11 @@ ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result)
 	default:
 	    return (EINVAL);
 	}
+	ATA_INTEL_LOCK(ctlr);
 	pci_write_config(parent, 0xa0,
 	    0x50 + smap[port] * 0x10 + reg * 4, 4);
 	*result = pci_read_config(parent, 0xa4, 4);
+	ATA_INTEL_UNLOCK(ctlr);
 	return (0);
 }
 
@@ -680,8 +697,10 @@ ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result)
 	default:
 	    return (EINVAL);
 	}
+	ATA_INTEL_LOCK(ctlr);
 	ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);
 	*result = ATA_IDX_INL(ch, ATA_IDX_DATA);
+	ATA_INTEL_UNLOCK(ctlr);
 	return (0);
 }
 
@@ -698,7 +717,7 @@ ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value)
 	ctlr = device_get_softc(parent);
 	ch = device_get_softc(dev);
 	port = (port == 1) ? 1 : 0;
-	smap = (u_char *)&ctlr->chipset_data + ch->unit * 2;
+	smap = ATA_INTEL_SMAP(ctlr, ch);
 	offset = 0x100 + smap[port] * 0x80;
 	switch (reg) {
 	case ATA_SSTATUS:
@@ -728,7 +747,7 @@ ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value)
 	parent = device_get_parent(dev);
 	ctlr = device_get_softc(parent);
 	ch = device_get_softc(dev);
-	smap = (u_char *)&ctlr->chipset_data + ch->unit * 2;
+	smap = ATA_INTEL_SMAP(ctlr, ch);
 	port = (port == 1) ? 1 : 0;
 	switch (reg) {
 	case ATA_SSTATUS:
@@ -743,9 +762,11 @@ ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value)
 	default:
 	    return (EINVAL);
 	}
+	ATA_INTEL_LOCK(ctlr);
 	pci_write_config(parent, 0xa0,
 	    0x50 + smap[port] * 0x10 + reg * 4, 4);
 	pci_write_config(parent, 0xa4, value, 4);
+	ATA_INTEL_UNLOCK(ctlr);
 	return (0);
 }
 
@@ -773,8 +794,10 @@ ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value)
 	default:
 	    return (EINVAL);
 	}
+	ATA_INTEL_LOCK(ctlr);
 	ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);
 	ATA_IDX_OUTL(ch, ATA_IDX_DATA, value);
+	ATA_INTEL_UNLOCK(ctlr);
 	return (0);
 }