On Sat, 3 Apr 1999, John S. Dyson wrote: > Alan Cox said: > > > > I've committed the basic infrastructure to improve TLB management > > on SMPs. Translation: this will lead to the elimination of a LOT > > of interprocessor interrupts to invalidate TLB entries. I'll be > > "turning on" the new mechanisms slowly so we can carefully debug > > each step and (hopefully) avoid any problems. > > > (To the rest of the team, Alan and Luoqi already know my opinion.) > > I just wanted to "chime in" and say that the new patches are based > on a really good concept, and is much cleaner than the previous > method. Also, many RISC architectures can utilize this > method due to the availability of lots of general registers. > (One could go so far as to have the compiler reserve the > register.) Non-threaded user mode apps could optionally > use the reserved register, but for threaded user mode apps, > that reserved register could also be used as a per-thread > base pointer. > > I believe that NT does the above (%fs for X86, and general > register for Alpha.) On PPC, there are several local, > per-processor registers that one could use (but loading a > general register with that per processor register would be > needed for access.) Also, since the PPC has lots of registers, > one could? permanently reserve one of the general registers (r13?). > > All in all, this change has the potential for better context > switching time (and less memory/better performance for multi-threaded > processes.) This is a serious, non-trivial movement in the *right* > direction!!! :-). SMP users should be pleased with this movement (I > certainly am!!!)
The alpha palcode supports a per-thread unique value which can be used by any threading system (user or kernel). -- Doug Rabson Mail: d...@nlsystems.com Nonlinear Systems Ltd. Phone: +44 181 442 9037 To Unsubscribe: send mail to majord...@freebsd.org with "unsubscribe freebsd-current" in the body of the message
