:On my system I can understand it, it's a 2xP5 with a shared L2 cache on a
:Neptune chipset - something that isn't known for speed. Once you get two
:processors hammering the system bus, *plus* mix in an EISA scsi
:controller, I could well imagine the memory bus getting thrashed.
When we started throwing together Duel-P-II machines, we basically
had to throw away our DEC chipset cards... I think that the DEC chip
cards, at least the older ones, have serious PCI spec bugs that cause
them to operate incorrectly on duel-cpu machines when more then one
cpu is populated.
-Matt
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