...
> > One question comes to mind: is there a way that the TSCs could become
> > desynchronized somehow? Even though all CPUs run at the same frequency,
> > isn't there a strong possibility for slight frequency deviation since
> > we use crystal oscillation instead of a more accurate atomic breakdown
> > for regulation, or am I just smoking crack?
>
> time for rehab, dude.
>
> since there is only a single master clock oscillator, there really
> should be no frequency difference between CPUs. There is the a phase
> difference caused by differences in conductor lengths between the
> master clock and the CPUs, but this difference is fixed by the length
> of the conductor and the laws of physics. Granted, all crystals have
> drift over time and temperature, but this drift should be identical
> for all CPUs on the same clock bus. Ideally, motherboards should be
> designed to have equal length clock lines to each CPU, thus
> eliminating this phase difference, especially with multiple selectable
> clock speeds which would change the wavelength, and thus the phase
> difference if the lines are of differing lengths.
And I would suspect if some one was to go look at the layout requirements
in Intel's design data for SMP boards you would find it is a requirement
that all CPU's in an SMP system have a very minimal phase skew in the
clock driven to the chip. How else are you going to run in sync with
the shared processor bus. I suspect that the allowed margin on the phase
of the clock pin is specified in pico seconds, and probably near 50 or so,
given the 100Mhz nature of this signal.
73 to KC5VDJ, KD7CAX
--
Rod Grimes - KD7CAX - (RWG25) [EMAIL PROTECTED]
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