On Tue, Jul 16, 2013 at 06:54:57PM +1000, Bruce Evans wrote: > ISTR disagreeing with jkim on using a special save area. I believe the normal save area cannot be used there at all, since the suspension is async and fpu.c could perform some operation on the PCB-pointed save area while suspend IPI is received.
> % /* Restore CR2, CR4, CR3 and CR0 */ > % ... > % movl PCB_CR0(%ecx),%eax > % movl %eax,%cr0 > % jmp 1f > % 1: > > What's this magic null jump? I think this is not needed. It seems to be an attempt to follow Intel spec, which requires to perform the long jump after enabling the paging, probably code got copied somehow from locore. The jmp is needed in i386/acpica/acpu_wakecode.S, but it is wrong there as well, since it should be a long jump. Also, the comment before the %cr0 manipulations to set CR0_PG was copied from amd64 version and is irrelevant there.
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