On Fri, November 25, 2011 13:57, Sergei Gorelkin wrote: > 24.11.2011 21:48, Florian Klämpfl пиŃĐľŃ: >> Am 24.11.2011 14:59, schrieb Sergei Gorelkin: . . >>> 5) What is the 'Athlon prefetch bug' we're trying to handle? Should be >>> an old thing, since it originates from svn revision 1; googling for >>> 'Athlon prefetch bug' does not give relevant information, and my >>> general >>> knowledge tells that such code should normally reside in OS kernel, not >>> in RTL. Anyway, does it apply to x86_64 target? >> >> Some old athlons, might include x86_64 ones, had a bug that sometimes >> prefetch (0^) causes a sig fault while it shouldn't, prefetch(0^) >> happens in the typical use case of prefetch: >> >> while assigned(p) do >> begin >> prefetch(p^.next^); >> ... >> ... >> p:=p^.next; >> end; > > This means no program using prefetch instructions could execute on such > CPU without similar > exception handling. Consequently, either Microsoft fixed it in next > service pack, or every complier > vendor would have to fix it independently (in which case it should become > much better known over the > Internet). We also don't have similar code in i386-linux RTL. > Maybe it is targeted to support some old Windows?
Isn't the fact that it's missing in i386-linux RTL more an omission of the respective platform maintainer rather than a hint that it might be specific to Windows (and specifically to old Windows)? Tomas _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
