On 06/23/2010 06:04 PM, Henry Vermaak wrote: > > That only means that it doesn't send the lock signal to the external > memory manager, so you can't have a multi processor implementation > using this processor. It doesn't affect the working of the swp > instruction. > I understand the "external memory manager" is the memory interface of the ARM IP core and thus is involved with any read and write access. As the ARM company only provides the CPU IP core, the chip manufacturer is responsible of the memory interface and if the locking is not decently handled, even a single CPU system might fail. This of course is true if the lock signal is provided by a more advanced ARM core but the Chip hardware does not use it
But maybe I am just too cautious .... -Michael _______________________________________________ fpc-devel maillist - [email protected] http://lists.freepascal.org/mailman/listinfo/fpc-devel
