On 06/23/2010 04:38 PM, Florian Klaempfl wrote: > > I can only speak for sparc (because I implemented them initially): they > are implemented according to official sparc docs. Do you know more then > them? >
Sorry if I have been sounding rude :(. I learned that If there is no hardware support, it's not possible to create thread-safe or smp safe atomic operations. Maybe the sequence in fact performs a "load locked, save conditional" paradigm, which I did not see. -Michael _______________________________________________ fpc-devel maillist - [email protected] http://lists.freepascal.org/mailman/listinfo/fpc-devel
