LGTM
Rémi Denis-Courmont <r...@remlab.net> 于2024年10月12日周六 13:38写道：
> The current triggers an illegal instruction if the CPU does not support
> vectors.
> ---
> libavcodec/riscv/vvc/vvcdsp_init.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/libavcodec/riscv/vvc/vvcdsp_init.c
> b/libavcodec/riscv/vvc/vvcdsp_init.c
> index 0a9f393259..30e8f59a58 100644
> --- a/libavcodec/riscv/vvc/vvcdsp_init.c
> +++ b/libavcodec/riscv/vvc/vvcdsp_init.c
> @@ -41,10 +41,13 @@ void ff_vvc_dsp_init_riscv(VVCDSPContext *const c,
> const int bd)
> {
> #if HAVE_RVV
> const int flags = av_get_cpu_flags();
> - int vlenb = ff_get_rv_vlenb();
> + int vlenb;
>
> - if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB) &&
> - vlenb >= 32) {
> + if (!(flags & AV_CPU_FLAG_RVV_I32) || !(flags & AV_CPU_FLAG_RVB))
> + return;
> +
> + vlenb = ff_get_rv_vlenb();
> + if (vlenb >= 32) {
> switch (bd) {
> case 8:
> c->inter.avg = ff_vvc_avg_8_rvv_256;
> @@ -55,8 +58,7 @@ void ff_vvc_dsp_init_riscv(VVCDSPContext *const c, const
> int bd)
> default:
> break;
> }
> - } else if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB)
> &&
> - vlenb >= 16) {
> + } else if (vlenb >= 16) {
> switch (bd) {
> case 8:
> c->inter.avg = ff_vvc_avg_8_rvv_128;
> --
> 2.45.2
>
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