While narrowing clip is nominally a rounding operation, the rounding mode
has no arithmetic consequence if the right shift is by zero bits.
---
libavcodec/riscv/h263dsp_rvv.S | 5 ++---
libavcodec/riscv/vp8dsp_rvv.S | 1 -
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/libavcodec/riscv/h263dsp_rvv.S b/libavcodec/riscv/h263dsp_rvv.S
index 97503d527c..2a57284e4b 100644
--- a/libavcodec/riscv/h263dsp_rvv.S
+++ b/libavcodec/riscv/h263dsp_rvv.S
@@ -30,14 +30,13 @@ func ff_h263_h_loop_filter_rvv, zve32x
vssseg4e8.v v8, (a0), a1
ret
1:
- csrwi vxrm, 0
-2: auipc t1, %pcrel_hi(ff_h263_loop_filter_strength)
+ auipc t1, %pcrel_hi(ff_h263_loop_filter_strength)
vwsubu.vv v14, v10, v9 # p2 - p1
add t1, t1, a2
vwsubu.vv v12, v8, v11 # p0 - p3
vsetvli zero, zero, e16, m1, ta, mu
vsll.vi v14, v14, 2
- lbu t1, %pcrel_lo(2b)(t1) # strength
+ lbu t1, %pcrel_lo(1b)(t1) # strength
vadd.vv v16, v12, v14
# Divide by 8 toward 0. v16 is a signed 10-bit value at this point.
vsrl.vi v18, v16, 16 - 3 # v18 = (v16 < 0) ? 7 : 0
diff --git a/libavcodec/riscv/vp8dsp_rvv.S b/libavcodec/riscv/vp8dsp_rvv.S
index 7e062d9f13..e50e27ce82 100644
--- a/libavcodec/riscv/vp8dsp_rvv.S
+++ b/libavcodec/riscv/vp8dsp_rvv.S
@@ -166,7 +166,6 @@ endfunc
# a3 = DC
func ff_vp78_idct_dc_add_rvv, zve32x
- csrwi vxrm, 0
vsetivli zero, 4, e8, mf4, ta, ma
sh zero, (a1)
vlse32.v v8, (a0), a2
--
2.45.2
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