From: Rémi Denis-Courmont <r...@remlab.net>
This adds a variant of the postfilter for use with 256-bit vectors (or
larger). Since the function requires 160-bit logical vectors, we can
cut the group multiplier down to just one.
The different vector type is passed via register. Unfortunately,
there is no VSETIVL instruction, so the constant vector size (5) also
needs to be passed via a register.
---
libavcodec/riscv/opusdsp_init.c | 17 ++++++++++++++---
libavcodec/riscv/opusdsp_rvv.S | 10 +++++++++-
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/libavcodec/riscv/opusdsp_init.c b/libavcodec/riscv/opusdsp_init.c
index 18d3892329..433b71e710 100644
--- a/libavcodec/riscv/opusdsp_init.c
+++ b/libavcodec/riscv/opusdsp_init.c
@@ -25,14 +25,25 @@
#include "libavutil/riscv/cpu.h"
#include "libavcodec/opusdsp.h"
-void ff_opus_postfilter_rvv(float *data, int period, float *gains, int len);
+void ff_opus_postfilter_rvv_32(float *data, int period, float *gains, int len);
+void ff_opus_postfilter_rvv_16(float *data, int period, float *gains, int len);
av_cold void ff_opus_dsp_init_riscv(OpusDSP *d)
{
#if HAVE_RVV
int flags = av_get_cpu_flags();
- if ((flags & AV_CPU_FLAG_RVV_I32) && ff_get_rv_vlenb() >= 16)
- d->postfilter = ff_opus_postfilter_rvv;
+ if (flags & AV_CPU_FLAG_RVV_I32)
+ switch (ff_get_rv_vlenb()) {
+ default:
+ d->postfilter = ff_opus_postfilter_rvv_32;
+ break;
+ case 16:
+ d->postfilter = ff_opus_postfilter_rvv_16;
+ break;
+ case 8:
+ case 4:
+ break;
+ }
#endif
}
diff --git a/libavcodec/riscv/opusdsp_rvv.S b/libavcodec/riscv/opusdsp_rvv.S
index f42a9c36c5..cfe332227e 100644
--- a/libavcodec/riscv/opusdsp_rvv.S
+++ b/libavcodec/riscv/opusdsp_rvv.S
@@ -21,7 +21,15 @@
#include "config.h"
#include "libavutil/riscv/asm.S"
-func ff_opus_postfilter_rvv, zve32f
+func ff_opus_postfilter_rvv_16, zve32f
+ lvtypei a5, e32, m2, ta, ma
+ j 1f
+endfunc
+
+func ff_opus_postfilter_rvv_32, zve32f
+ lvtypei a5, e32, m1, ta, ma
+1:
+ li a4, 5
addi a1, a1, 2
slli a1, a1, 2
sh2add a3, a3, a0
--
2.37.2
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