Hi,
Hope your are doing good. Please share me profiles to md.kh...@3sbc.com <chandra....@3sbc.com> *Requirement:* Sr. FPGA Design Engineer *No of Positions*: 1 *Requirement Locations*: Stamford, CT *Job Description:* *What You Will Do :* · Determine architecture, system verification and detailed design approach · Define module interfaces and all aspects of device design and simulation coordinated with the PC Board Designers · Evaluate the process flow including but not limited to high level design, synthesis, place and route, timing constraints and power utilization · Develop test, simulation plans and design verification test plans at design top level · Develop, implement and supervise design verification test plans at system level. · Support the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the FPGA development life cycle · May provide leadership and/or direction to lower level employees · Independently determine approach to solutions and get alignment from System Engineers and board developers · Contribute to design and development of FPGA hardware for control, communications systems and digital signal processing (DSP) platforms. *What You Need :* ??? · Highly proficient use and understanding of FPGA engineering concepts, principles, and theories · Highly proficient in FPGA design languages and tools including VHDL and UVM or OSVVM · Altera High Level Synthesis is preferred · Experience with FPGA development software - Modelsim, Quartus, Mentor CDC a plus · Highly proficient in Microsoft Office applications · Excellent communication skills: identifying issues, impacts, and corrective actions · Experience with FPGA SoC, including Avalon and AXI architectures · Experience with architecting and implementing embedded processors including NIOS · Proficient in implementing IP blocks based on interface requirements and designing the required interface logic to overall FPGA architecture · Expertise using VHDL for implementation and verification of FPGA designs · Basic knowledge of signal algorithms · VHDL, System Verilog, UVM · Questa Sim, Modelsim, Quartus · GIT, JIRA · MATLAB and SimuLink Regards, *Md.Khazababu* Recruiter 3*S* Business Corporation Inc(*3SBC*) P: 281-823-9222 Ext 518 | F: 281-823-9225 Email: md.kh...@3sbc.com| <meena.bhu...@3sbc.com%7C> www.3sbc.com Hangouts – khaza3...@gmail.com <meena.bhusara3...@gmail.com%7C%20Skype> *3S Business Corporation Inc. 11271 Richmond Ave, Suite # H107, # H108 Houston, Texas. 77082* -- Are you =EXP(E:RT) or =NOT(EXP(E:RT)) in Excel? And do you wanna be? It’s =TIME(2,DO:IT,N:OW) ! Join official Facebook page of this forum @ https://www.facebook.com/discussexcel FORUM RULES 1) Use concise, accurate thread titles. Poor thread titles, like Please Help, Urgent, Need Help, Formula Problem, Code Problem, and Need Advice will not get quick attention or may not be answered. 2) Don't post a question in the thread of another member. 3) Don't post questions regarding breaking or bypassing any security measure. 4) Acknowledge the responses you receive, good or bad. 5) Jobs posting is not allowed. 6) Sharing copyrighted material and their links is not allowed. NOTE : Don't ever post confidential data in a workbook. Forum owners and members are not responsible for any loss. --- You received this message because you are subscribed to the Google Groups "MS EXCEL AND VBA MACROS" group. To unsubscribe from this group and stop receiving emails from it, send an email to excel-macros+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/excel-macros/CAKPjPOT4W7hxMiDa00O5TrV-5MjpGiQue7sRLqQX-Pr7KoX%2BEg%40mail.gmail.com.
