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commit 3ae0e188bc36e63b0f1037a32582d1b386e4a218
Author: [email protected] <[email protected]>
AuthorDate: Mon Aug 3 21:15:55 2026 -0600
evas: port blend pixel+colour group to AVX2 with a 4-wide stage
Adds op_blend_pixel_color_avx2.c with all six span kernels and their
aliases ported from op_blend_pixel_color_sse3.c, plus the four helpers
they need (mul_sym_avx2, mul4_sym_avx2, mul3_sym_avx2,
interp4_256_avx2) in evas_blend_ops.h.
Initially only the SC_AA (_caa_) family (6 slots) could be registered:
it is bit-exact against the C reference (maxdelta=0), backed by
mul_256_avx2 and interp4_256_avx2. The SC/SC_AN (_c_/_can_) family (12
slots) ported and compiled, but was left unregistered - it depends on
mul4_sym_avx2/mul3_sym_avx2, which reproduce mul4_sym_sse3's G-channel
rounding exactly (verified with a standalone differential harness
against 200k random inputs), and mul4_sym_sse3 itself is not
bit-exact against the plain-C MUL4_SYM macro (~78% mismatch rate at
delta 1, pre-existing in the shipped SSE3 code, not introduced here).
Re-checked against evas_avx2_vs_sse3_ops once that harness existed,
per the corrected acceptance bar (match SSE3, not C, where SSE3
already has a kernel): still not bit-exact, for a second, independent
reason. mul4_sym_avx2 is bit-identical to mul4_sym_sse3 in isolation,
but LOOP_ALIGNED_U1_A8_A16 (AVX2) only vectorised at >=8 pixels while
LOOP_ALIGNED_U1_A48 (SSE3) vectorises at >=4, so a 4-7 pixel span took
AVX2's C-matching scalar path but SSE3's rounding-approximate vector
path - the two tiers disagreed at exactly those lengths even though
their vector arithmetic matches perfectly once both sides vectorise.
Neither reference cleared the bar for these 12 slots on the first
pass.
Fixed by closing the boundary gap rather than loosening the bar.
LOOP_ALIGNED_U1_A8_A16 is replaced with LOOP_ALIGNED_U1_A4_A8_A16 in
evas_blend_ops.h: scalar prologue to 16-byte alignment (matching
LOOP_ALIGNED_U1_A48's own prologue pixel-for-pixel), then - if still
short of 32-byte alignment and >=4 pixels remain - one corrective
4-wide block to reach the alignment _mm256_load/store_si256 need,
then the existing 16/8/4/scalar cascade. An intermediate version that
kept a 32-byte-only prologue and just added an A4OP case still failed
evas_avx2_vs_sse3_ops at len=4 spans whose address was 16- but not
32-byte aligned: the whole span was consumed as scalar before any
vector op ran. The two-stage prologue fixes that by drawing the
scalar/vector line at the same pixel SSE3 draws it. Every AVX2 kernel
(pixel, colour, pixel+colour) gets a 4-wide A4OP stage using the SSE3
kernel's A4OP body verbatim (__m128i, _sse3 helpers), so AVX2 executes
literally the same instructions SSE3 does at 4-7 pixels; this needs
the SSE3 helpers and their mask constants in the AVX2 translation
unit, so op_blend_master_avx2.c now defines NEED_SSE3 and initialises
its own per-TU copies of GA_MASK_SSE3/RB_MASK_SSE3/SYM4_MASK_SSE3/
RGB_MASK_SSE3/A_MASK_SSE3/ALPHA_SSE3 (op_blend_master_sse3.c's copies
do not reach this TU).
All 18 pixel+colour slots are now registered, mirroring
init_blend_pixel_color_span_funcs_sse3 exactly. evas_avx2_vs_sse3_ops:
pair count 11 -> 23 (+12), differing pixels 0, maxdelta 0 - bit-exact
at every length. evas_avx2_ops (vs C): the 12 _c_/_can_ slots now
legitimately show maxdelta=1 (they match SSE3's approximation at
every length, including 4-7px, which is a divergence from C by
construction, not a regression); the mul_256-based slots (pixel,
colour) remain bit-exact against C.
Measured with expedite (buffer engine), median of 3 runs per tier at 20
loops per test, on an -O2 build. AVX2 was selected by leaving
EVAS_CPU_NO_AVX2 unset; the SSE3 baseline was selected by setting it.
Note EVAS_CPU_NO_AVX2 is tested by presence, not value - setting it to 0
still disables AVX2, it must be left unset to enable AVX2.
Tests 3/4/17: +15%, +10%, +70%, geometric mean +29% (up from +25% with
only the 6 SC_AA slots live).
Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>
---
.../common/evas_op_blend/op_blend_color_avx2.c | 24 +-
.../common/evas_op_blend/op_blend_master_avx2.c | 40 ++
.../common/evas_op_blend/op_blend_pixel_avx2.c | 25 +-
.../evas_op_blend/op_blend_pixel_color_avx2.c | 462 +++++++++++++++++++++
src/lib/evas/include/evas_blend_ops.h | 193 ++++++++-
5 files changed, 730 insertions(+), 14 deletions(-)
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_color_avx2.c b/src/lib/evas/common/evas_op_blend/op_blend_color_avx2.c
index c11baa26a7..f9a47539b0 100644
--- a/src/lib/evas/common/evas_op_blend/op_blend_color_avx2.c
+++ b/src/lib/evas/common/evas_op_blend/op_blend_color_avx2.c
@@ -5,11 +5,16 @@
* aliases), at one arithmetic shape - constant colour blended over dest, no
* source pointer, no mask. A bit-exact pass here validates the porting
* pattern (mul_256_avx2 as a lane-local port of the SSE3 helper) and the
- * LOOP_ALIGNED_U1_A8_A16 alignment handling for colour-only blends. It does
- * NOT validate any other arithmetic shape - pixel/mask blends, the
+ * LOOP_ALIGNED_U1_A4_A8_A16 alignment handling for colour-only blends. It
+ * does NOT validate any other arithmetic shape - pixel/mask blends, the
* relative-blend variants, etc. Later kernel groups that copy this file's
* pattern each need their own differential-test run against their own C
* reference; none of that verification can be inherited from this result.
+ *
+ * The A4OP block is the SSE3 kernel's A4OP body verbatim (__m128i, _sse3
+ * helpers): the 4-wide stage exists so AVX2 executes the same instructions
+ * SSE3 does at 4-7 pixels. mul_256_sse3 is exact against plain C at every
+ * width, so this doesn't change this kernel's bit-exactness against C.
*/
#ifdef BUILD_AVX2
@@ -21,13 +26,26 @@ _op_blend_c_dp_avx2(DATA32 *s EINA_UNUSED, DATA8 *m EINA_UNUSED, DATA32 c, DATA3
const __m256i c_packed = _mm256_set1_epi32(c);
const __m256i a_packed = _mm256_set1_epi32(a);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+ const __m128i a_packed128 = _mm_set_epi32(a, a, a, a);
- LOOP_ALIGNED_U1_A8_A16(d, l,
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
{ /* UOP */
*d = c + MUL_256(a, *d);
d++; l--;
},
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i d0 = _mm_load_si128((__m128i *)d);
+
+ d0 = mul_256_sse3(a_packed128, d0);
+ d0 = _mm_add_epi32(d0, c_packed128);
+
+ _mm_store_si128((__m128i *)d, d0);
+
+ d += 4; l -= 4;
+ },
{ /* A8OP */
__m256i d0 = _mm256_load_si256((__m256i *)d);
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_master_avx2.c b/src/lib/evas/common/evas_op_blend/op_blend_master_avx2.c
index 8bcd1e9496..180817290f 100644
--- a/src/lib/evas/common/evas_op_blend/op_blend_master_avx2.c
+++ b/src/lib/evas/common/evas_op_blend/op_blend_master_avx2.c
@@ -9,6 +9,13 @@
#define NEED_AVX2 1
+/* Also need the SSE3 helpers (mul4_sym_sse3, mul3_sym_sse3, mul_256_sse3,
+ * sub4_alpha_sse3, interp4_256_sse3): the 4-wide stage in every kernel in
+ * this TU runs the SSE3 kernel's A4OP body verbatim, so AVX2 and SSE3
+ * execute literally the same instructions at 4-7 pixels rather than merely
+ * equivalent ones (see LOOP_ALIGNED_U1_A4_A8_A16 in evas_blend_ops.h). */
+#define NEED_SSE3 1
+
#include "Eina.h"
#include "Evas.h"
#include "evas_common_types.h"
@@ -18,11 +25,28 @@ EXPORTAPI void evas_common_cpu_end_opt(void);
#include "config.h"
#include "evas_blend_ops.h"
+#ifdef BUILD_AVX2
+static __m256i A_MASK_AVX2;
+#endif
+
+/* CRITICAL: the SSE3 statics (GA_MASK_SSE3, RB_MASK_SSE3, SYM4_MASK_SSE3,
+ * RGB_MASK_SSE3, ALPHA_SSE3, A_MASK_SSE3) declared by evas_blend_ops.h and
+ * below are per-translation-unit. op_blend_master_sse3.c initialises ITS
+ * own copies in evas_common_op_blend_init_sse3() - that does NOT reach this
+ * TU's separate, zero-initialised copies. If evas_common_op_blend_init_avx2()
+ * below did not set them too, every 4-wide block in this TU would multiply
+ * against zero masks and produce garbage. Values copied verbatim from
+ * op_blend_master_sse3.c; keep them in sync if that file's ever change. */
+#ifdef BUILD_SSE3
+static __m128i A_MASK_SSE3;
+#endif
+
extern RGBA_Gfx_Func op_blend_span_funcs[SP_LAST][SM_LAST][SC_LAST][DP_LAST][CPU_LAST];
extern RGBA_Gfx_Func op_blend_rel_span_funcs[SP_LAST][SM_LAST][SC_LAST][DP_LAST][CPU_LAST];
# include "op_blend_pixel_avx2.c"
# include "op_blend_color_avx2.c"
+# include "op_blend_pixel_color_avx2.c"
void
evas_common_op_blend_init_avx2(void)
@@ -31,9 +55,25 @@ evas_common_op_blend_init_avx2(void)
GA_MASK_AVX2 = _mm256_set1_epi32(0x00FF00FF);
RB_MASK_AVX2 = _mm256_set1_epi32(0xFF00FF00);
ALPHA_AVX2 = _mm256_set1_epi32(256);
+ SYM4_MASK_AVX2 = _mm256_set_epi32(0x00FF00FF, 0x000000FF, 0x00FF00FF, 0x000000FF, 0x00FF00FF, 0x000000FF, 0x00FF00FF, 0x000000FF);
+ RGB_MASK_AVX2 = _mm256_set1_epi32(0xFFFFFF);
+ A_MASK_AVX2 = _mm256_set1_epi32(0xFF000000);
+
+#ifdef BUILD_SSE3
+ /* This TU's own copies of the SSE3 constants, for the 4-wide stage - see
+ * the CRITICAL comment above. Values must match
+ * evas_common_op_blend_init_sse3() in op_blend_master_sse3.c exactly. */
+ GA_MASK_SSE3 = _mm_set_epi32(0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF);
+ RB_MASK_SSE3 = _mm_set_epi32(0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00);
+ SYM4_MASK_SSE3 = _mm_set_epi32(0x00FF00FF, 0x000000FF, 0x00FF00FF, 0x000000FF);
+ RGB_MASK_SSE3 = _mm_set_epi32(0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF);
+ A_MASK_SSE3 = _mm_set_epi32(0xFF000000, 0xFF000000, 0xFF000000, 0xFF000000);
+ ALPHA_SSE3 = _mm_set_epi32(256, 256, 256, 256);
+#endif
init_blend_pixel_span_funcs_avx2();
init_blend_color_span_funcs_avx2();
+ init_blend_pixel_color_span_funcs_avx2();
#endif
}
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_pixel_avx2.c b/src/lib/evas/common/evas_op_blend/op_blend_pixel_avx2.c
index 664c9b1004..fd3d267822 100644
--- a/src/lib/evas/common/evas_op_blend/op_blend_pixel_avx2.c
+++ b/src/lib/evas/common/evas_op_blend/op_blend_pixel_avx2.c
@@ -5,11 +5,19 @@
* SP_AS alias), at one arithmetic shape - plain premultiplied source blended
* over dest, no mask, no colour. A bit-exact pass here validates the porting
* pattern (mul_256_avx2/sub4_alpha_avx2 as lane-local ports of the SSE3
- * helpers) and the LOOP_ALIGNED_U1_A8_A16 alignment handling. It does NOT
+ * helpers) and the LOOP_ALIGNED_U1_A4_A8_A16 alignment handling. It does NOT
* validate any other arithmetic shape - mask blends, colour blends, the
* relative-blend variants, etc. Later kernel groups that copy this file's
* pattern each need their own differential-test run against their own C
* reference; none of that verification can be inherited from this result.
+ *
+ * The A4OP block below is the SSE3 kernel's A4OP body verbatim (__m128i,
+ * _sse3 helpers) rather than a 128-bit-narrowed AVX2 port: the point of the
+ * 4-wide stage is for AVX2 to execute literally the same instructions SSE3
+ * does at 4-7 pixels, not merely equivalent ones. mul_256_sse3 is exact
+ * against plain C at every width, so this doesn't change this kernel's
+ * bit-exactness against C; it matters for kernels elsewhere in this group
+ * whose SSE3 helpers are not exact against C (see op_blend_pixel_color_avx2.c).
*/
#ifdef BUILD_AVX2
@@ -17,13 +25,26 @@
static void
_op_blend_p_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c EINA_UNUSED, DATA32 *d, int l) {
- LOOP_ALIGNED_U1_A8_A16(d, l,
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
{ /* UOP */
int alpha = 256 - (*s >> 24);
*d = *s + MUL_256(alpha, *d);
s++; d++; l--;
},
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+ __m128i d0 = _mm_load_si128((__m128i *)d);
+
+ __m128i a0 = sub4_alpha_sse3(s0);
+ __m128i mul0 = mul_256_sse3(a0, d0);
+ d0 = _mm_add_epi32(mul0, s0);
+
+ _mm_store_si128((__m128i *)d, d0);
+
+ s += 4; d += 4; l -= 4;
+ },
{ /* A8OP */
__m256i s0 = _mm256_loadu_si256((__m256i *)s);
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_pixel_color_avx2.c b/src/lib/evas/common/evas_op_blend/op_blend_pixel_color_avx2.c
new file mode 100644
index 0000000000..723731dc70
--- /dev/null
+++ b/src/lib/evas/common/evas_op_blend/op_blend_pixel_color_avx2.c
@@ -0,0 +1,462 @@
+/* blend pixel x color --> dst */
+
+/* Validated against SSE3, not against the plain-C reference, for the SC/
+ * SC_AN kernels (_c_/_can_, built on mul4_sym_avx2/mul3_sym_avx2). SSE3's
+ * mul4_sym/mul3_sym round the G channel differently from the plain-C
+ * MUL4_SYM/MUL3_SYM macros (1 LSB, most inputs) - a pre-existing property
+ * of the shipped SSE3 algorithm, not something introduced by this port.
+ * Since AVX2 is meant to be a drop-in replacement for SSE3 (same op table,
+ * same slot), the correct target is bit-exact-with-SSE3, and maxdelta=1
+ * against plain C for these slots is therefore expected, not a regression.
+ *
+ * Every kernel in this file uses a 4-wide __m128i stage
+ * (LOOP_ALIGNED_U1_A4_A8_A16's A4OP), the SSE3 kernel's A4OP body verbatim.
+ * Without it, a 4-7 pixel span ran through AVX2's scalar UOP (exact against
+ * C) while the same span on SSE3 ran through SSE3's vector A4OP (carrying
+ * the G-channel rounding gap above), so the two tiers disagreed with each
+ * other at exactly those lengths even though their 8/16-wide vector
+ * arithmetic matches once both sides are actually vectorising - see the
+ * LOOP_ALIGNED_U1_A4_A8_A16 comment in evas_blend_ops.h for the mechanism.
+ *
+ * The SC_AA kernels (mul_256_avx2, interp4_256_avx2) have no rounding gap at
+ * any width and are bit-exact against both C and SSE3, with or without the
+ * 4-wide stage; it is present for them too, for consistency.
+ */
+
+#ifdef BUILD_AVX2
+
+static void
+_op_blend_p_c_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c, DATA32 *d, int l) {
+
+ DATA32 alpha;
+
+ const __m256i c_packed = _mm256_set1_epi32(c);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
+ { /* UOP */
+
+ DATA32 sc = MUL4_SYM(c, *s);
+ alpha = 256 - (sc >> 24);
+ *d = sc + MUL_256(alpha, *d);
+ d++; s++; l--;
+ },
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+ __m128i d0 = _mm_load_si128((__m128i *)d);
+
+ __m128i sc0 = mul4_sym_sse3(c_packed128, s0);
+ __m128i a0 = sub4_alpha_sse3(sc0);
+ __m128i mul0 = mul_256_sse3(a0, d0);
+
+ d0 = _mm_add_epi32(sc0, mul0);
+
+ _mm_store_si128((__m128i *)d, d0);
+
+ d += 4; s += 4; l -= 4;
+ },
+ { /* A8OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i sc0 = mul4_sym_avx2(c_packed, s0);
+ __m256i a0 = sub4_alpha_avx2(sc0);
+ __m256i mul0 = mul_256_avx2(a0, d0);
+
+ d0 = _mm256_add_epi32(sc0, mul0);
+
+ _mm256_store_si256((__m256i *)d, d0);
+
+ d += 8; s += 8; l -= 8;
+ },
+ { /* A16OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i s1 = _mm256_loadu_si256((__m256i *)(s+8));
+ __m256i d1 = _mm256_load_si256((__m256i *)(d+8));
+
+ __m256i sc0 = mul4_sym_avx2(c_packed, s0);
+ __m256i sc1 = mul4_sym_avx2(c_packed, s1);
+
+ __m256i a0 = sub4_alpha_avx2(sc0);
+ __m256i a1 = sub4_alpha_avx2(sc1);
+
+ __m256i mul0 = mul_256_avx2(a0, d0);
+ __m256i mul1 = mul_256_avx2(a1, d1);
+
+ d0 = _mm256_add_epi32(sc0, mul0);
+ d1 = _mm256_add_epi32(sc1, mul1);
+
+ _mm256_store_si256((__m256i *)d, d0);
+ _mm256_store_si256((__m256i *)(d+8), d1);
+
+ d += 16; s += 16; l -= 16;
+ })
+}
+
+static void
+_op_blend_pan_c_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c, DATA32 *d, int l) {
+
+ DATA32 c_a = c & 0xFF000000;
+ DATA32 alpha = 256 - (c >> 24);
+
+ const __m256i c_packed = _mm256_set1_epi32(c);
+ const __m256i c_alpha = _mm256_set1_epi32(c_a);
+ const __m256i a0v = _mm256_set1_epi32(alpha);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+ const __m128i c_alpha128 = _mm_set_epi32(c_a, c_a, c_a, c_a);
+ const __m128i a0v128 = _mm_set_epi32(alpha, alpha, alpha, alpha);
+
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
+ { /* UOP */
+
+ *d = ((c & 0xff000000) + MUL3_SYM(c, *s)) + MUL_256(alpha, *d);
+ d++; s++; l--;
+ },
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+ __m128i d0 = _mm_load_si128((__m128i *)d);
+
+ __m128i r0 = _mm_add_epi32(mul3_sym_sse3(c_packed128, s0),
+ mul_256_sse3(a0v128, d0));
+
+ r0 = _mm_add_epi32(r0, c_alpha128);
+
+ _mm_store_si128((__m128i *)d, r0);
+
+ d += 4; s += 4; l -= 4;
+ },
+ { /* A8OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i r0 = _mm256_add_epi32(mul3_sym_avx2(c_packed, s0),
+ mul_256_avx2(a0v, d0));
+
+ r0 = _mm256_add_epi32(r0, c_alpha);
+
+ _mm256_store_si256((__m256i *)d, r0);
+
+ d += 8; s += 8; l -= 8;
+ },
+ { /* A16OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i s1 = _mm256_loadu_si256((__m256i *)(s+8));
+ __m256i d1 = _mm256_load_si256((__m256i *)(d+8));
+
+ __m256i r0 = _mm256_add_epi32(mul3_sym_avx2(c_packed, s0),
+ mul_256_avx2(a0v, d0));
+
+ __m256i r1 = _mm256_add_epi32(mul3_sym_avx2(c_packed, s1),
+ mul_256_avx2(a0v, d1));
+
+ r0 = _mm256_add_epi32(r0, c_alpha);
+ r1 = _mm256_add_epi32(r1, c_alpha);
+
+ _mm256_store_si256((__m256i *)d, r0);
+ _mm256_store_si256((__m256i *)(d+8), r1);
+
+ d += 16; s += 16; l -= 16;
+ })
+}
+
+static void
+_op_blend_p_can_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c, DATA32 *d, int l) {
+
+ int alpha;
+ const __m256i c_packed = _mm256_set1_epi32(c);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
+ { /* UOP */
+
+ alpha = 256 - (*s >> 24);
+ *d = ((*s & 0xff000000) + MUL3_SYM(c, *s)) + MUL_256(alpha, *d);
+ d++; s++; l--;
+ },
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+ __m128i d0 = _mm_load_si128((__m128i *)d);
+
+ __m128i a0 = sub4_alpha_sse3(s0);
+
+ __m128i r0 = _mm_add_epi32(mul3_sym_sse3(c_packed128, s0),
+ mul_256_sse3(a0, d0));
+
+ r0 = _mm_add_epi32(r0, _mm_and_si128(s0, A_MASK_SSE3));
+
+ _mm_store_si128((__m128i *)d, r0);
+
+ d += 4; s += 4; l -= 4;
+ },
+ { /* A8OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i a0 = sub4_alpha_avx2(s0);
+
+ __m256i r0 = _mm256_add_epi32(mul3_sym_avx2(c_packed, s0),
+ mul_256_avx2(a0, d0));
+
+ r0 = _mm256_add_epi32(r0, _mm256_and_si256(s0, A_MASK_AVX2));
+
+ _mm256_store_si256((__m256i *)d, r0);
+
+ d += 8; s += 8; l -= 8;
+ },
+ { /* A16OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i s1 = _mm256_loadu_si256((__m256i *)(s+8));
+ __m256i d1 = _mm256_load_si256((__m256i *)(d+8));
+
+ __m256i a0 = sub4_alpha_avx2(s0);
+ __m256i a1 = sub4_alpha_avx2(s1);
+
+ __m256i r0 = _mm256_add_epi32(mul3_sym_avx2(c_packed, s0),
+ mul_256_avx2(a0, d0));
+
+ __m256i r1 = _mm256_add_epi32(mul3_sym_avx2(c_packed, s1),
+ mul_256_avx2(a1, d1));
+
+ r0 = _mm256_add_epi32(r0, _mm256_and_si256(s0, A_MASK_AVX2));
+ r1 = _mm256_add_epi32(r1, _mm256_and_si256(s1, A_MASK_AVX2));
+
+ _mm256_store_si256((__m256i *)d, r0);
+ _mm256_store_si256((__m256i *)(d+8), r1);
+
+ d += 16; s += 16; l -= 16;
+ })
+}
+
+static void
+_op_blend_pan_can_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c, DATA32 *d, int l) {
+
+ const __m256i c_packed = _mm256_set1_epi32(c);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
+ { /* UOP */
+
+ *d++ = 0xff000000 + MUL3_SYM(c, *s);
+ s++; l--;
+ },
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+
+ __m128i r0 = mul3_sym_sse3(c_packed128, s0);
+ r0 = _mm_add_epi32(r0, A_MASK_SSE3);
+
+ _mm_store_si128((__m128i *)d, r0);
+
+ d += 4; s += 4; l -= 4;
+ },
+ { /* A8OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+
+ __m256i r0 = mul3_sym_avx2(c_packed, s0);
+ r0 = _mm256_add_epi32(r0, A_MASK_AVX2);
+
+ _mm256_store_si256((__m256i *)d, r0);
+
+ d += 8; s += 8; l -= 8;
+ },
+ { /* A16OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i s1 = _mm256_loadu_si256((__m256i *)(s+8));
+
+ __m256i r0 = mul3_sym_avx2(c_packed, s0);
+ __m256i r1 = mul3_sym_avx2(c_packed, s1);
+
+ r0 = _mm256_add_epi32(r0, A_MASK_AVX2);
+ r1 = _mm256_add_epi32(r1, A_MASK_AVX2);
+
+ _mm256_store_si256((__m256i *)d, r0);
+ _mm256_store_si256((__m256i *)(d+8), r1);
+
+ d += 16; s += 16; l -= 16;
+ })
+}
+
+static void
+_op_blend_p_caa_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c, DATA32 *d, int l) {
+
+ int alpha;
+ c = 1 + (c & 0xff);
+ const __m256i c_packed = _mm256_set1_epi32(c);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
+ { /* UOP */
+
+ DATA32 sc = MUL_256(c, *s);
+ alpha = 256 - (sc >> 24);
+ *d = sc + MUL_256(alpha, *d);
+ d++;
+ s++;
+ l--;
+ },
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+ __m128i d0 = _mm_load_si128 ((__m128i *)d);
+
+ __m128i sc0 = mul_256_sse3(c_packed128, s0);
+ __m128i a0 = sub4_alpha_sse3(sc0);
+
+ __m128i r0 = _mm_add_epi32(mul_256_sse3(a0, d0), sc0);
+
+ _mm_store_si128((__m128i *)d, r0);
+
+ d += 4; s += 4; l -= 4;
+ },
+ { /* A8OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256 ((__m256i *)d);
+
+ __m256i sc0 = mul_256_avx2(c_packed, s0);
+ __m256i a0 = sub4_alpha_avx2(sc0);
+
+ __m256i r0 = _mm256_add_epi32(mul_256_avx2(a0, d0), sc0);
+
+ _mm256_store_si256((__m256i *)d, r0);
+
+ d += 8; s += 8; l -= 8;
+ },
+ { /* A16OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i s1 = _mm256_loadu_si256((__m256i *)(s+8));
+ __m256i d1 = _mm256_load_si256((__m256i *)(d+8));
+
+ __m256i sc0 = mul_256_avx2(c_packed, s0);
+ __m256i sc1 = mul_256_avx2(c_packed, s1);
+
+ __m256i a0 = sub4_alpha_avx2(sc0);
+ __m256i a1 = sub4_alpha_avx2(sc1);
+
+ __m256i r0 = _mm256_add_epi32(mul_256_avx2(a0, d0), sc0);
+ __m256i r1 = _mm256_add_epi32(mul_256_avx2(a1, d1), sc1);
+
+ _mm256_store_si256((__m256i *)d, r0);
+ _mm256_store_si256((__m256i *)(d+8), r1);
+
+ d += 16; s += 16; l -= 16;
+ })
+}
+
+static void
+_op_blend_pan_caa_dp_avx2(DATA32 *s, DATA8 *m EINA_UNUSED, DATA32 c, DATA32 *d, int l) {
+
+ c = 1 + (c & 0xff);
+ const __m256i c_packed = _mm256_set1_epi32(c);
+ const __m128i c_packed128 = _mm_set_epi32(c, c, c, c);
+
+ LOOP_ALIGNED_U1_A4_A8_A16(d, l,
+ { /* UOP */
+
+ *d = INTERP_256(c, *s, *d);
+ d++; s++; l--;
+ },
+ { /* A4OP - verbatim SSE3 A4OP body, see file header */
+
+ __m128i s0 = _mm_lddqu_si128((__m128i *)s);
+ __m128i d0 = _mm_load_si128((__m128i *)d);
+
+ __m128i r0 = interp4_256_sse3(c_packed128, s0, d0);
+
+ _mm_store_si128((__m128i *)d, r0);
+
+ d += 4; s += 4; l -= 4;
+ },
+ { /* A8OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i r0 = interp4_256_avx2(c_packed, s0, d0);
+
+ _mm256_store_si256((__m256i *)d, r0);
+
+ d += 8; s += 8; l -= 8;
+ },
+ { /* A16OP */
+
+ __m256i s0 = _mm256_loadu_si256((__m256i *)s);
+ __m256i d0 = _mm256_load_si256((__m256i *)d);
+
+ __m256i s1 = _mm256_loadu_si256((__m256i *)(s+8));
+ __m256i d1 = _mm256_load_si256((__m256i *)(d+8));
+
+ __m256i r0 = interp4_256_avx2(c_packed, s0, d0);
+ __m256i r1 = interp4_256_avx2(c_packed, s1, d1);
+
+ _mm256_store_si256((__m256i *)d, r0);
+ _mm256_store_si256((__m256i *)(d+8), r1);
+
+ d += 16; s += 16; l -= 16;
+ })
+}
+
+#define _op_blend_pas_c_dp_avx2 _op_blend_p_c_dp_avx2
+#define _op_blend_pas_can_dp_avx2 _op_blend_p_can_dp_avx2
+#define _op_blend_pas_caa_dp_avx2 _op_blend_p_caa_dp_avx2
+
+#define _op_blend_p_c_dpan_avx2 _op_blend_p_c_dp_avx2
+#define _op_blend_pas_c_dpan_avx2 _op_blend_pas_c_dp_avx2
+#define _op_blend_pan_c_dpan_avx2 _op_blend_pan_c_dp_avx2
+#define _op_blend_p_can_dpan_avx2 _op_blend_p_can_dp_avx2
+#define _op_blend_pas_can_dpan_avx2 _op_blend_pas_can_dp_avx2
+#define _op_blend_pan_can_dpan_avx2 _op_blend_pan_can_dp_avx2
+#define _op_blend_p_caa_dpan_avx2 _op_blend_p_caa_dp_avx2
+#define _op_blend_pas_caa_dpan_avx2 _op_blend_pas_caa_dp_avx2
+#define _op_blend_pan_caa_dpan_avx2 _op_blend_pan_caa_dp_avx2
+
+static void
+init_blend_pixel_color_span_funcs_avx2(void)
+{
+ /* All 18 slots, mirroring init_blend_pixel_color_span_funcs_sse3 exactly.
+ * Bit-exact against SSE3 at every length (evas_avx2_vs_sse3_ops: 0 diff,
+ * maxdelta=0). The SC/SC_AN slots legitimately show maxdelta=1 against
+ * plain C (evas_avx2_ops) - see the file header. */
+ op_blend_span_funcs[SP][SM_N][SC][DP][CPU_AVX2] = _op_blend_p_c_dp_avx2;
+ op_blend_span_funcs[SP_AS][SM_N][SC][DP][CPU_AVX2] = _op_blend_pas_c_dp_avx2;
+ op_blend_span_funcs[SP_AN][SM_N][SC][DP][CPU_AVX2] = _op_blend_pan_c_dp_avx2;
+ op_blend_span_funcs[SP][SM_N][SC_AN][DP][CPU_AVX2] = _op_blend_p_can_dp_avx2;
+ op_blend_span_funcs[SP_AS][SM_N][SC_AN][DP][CPU_AVX2] = _op_blend_pas_can_dp_avx2;
+ op_blend_span_funcs[SP_AN][SM_N][SC_AN][DP][CPU_AVX2] = _op_blend_pan_can_dp_avx2;
+ op_blend_span_funcs[SP][SM_N][SC_AA][DP][CPU_AVX2] = _op_blend_p_caa_dp_avx2;
+ op_blend_span_funcs[SP_AS][SM_N][SC_AA][DP][CPU_AVX2] = _op_blend_pas_caa_dp_avx2;
+ op_blend_span_funcs[SP_AN][SM_N][SC_AA][DP][CPU_AVX2] = _op_blend_pan_caa_dp_avx2;
+
+ op_blend_span_funcs[SP][SM_N][SC][DP_AN][CPU_AVX2] = _op_blend_p_c_dpan_avx2;
+ op_blend_span_funcs[SP_AS][SM_N][SC][DP_AN][CPU_AVX2] = _op_blend_pas_c_dpan_avx2;
+ op_blend_span_funcs[SP_AN][SM_N][SC][DP_AN][CPU_AVX2] = _op_blend_pan_c_dpan_avx2;
+ op_blend_span_funcs[SP][SM_N][SC_AN][DP_AN][CPU_AVX2] = _op_blend_p_can_dpan_avx2;
+ op_blend_span_funcs[SP_AS][SM_N][SC_AN][DP_AN][CPU_AVX2] = _op_blend_pas_can_dpan_avx2;
+ op_blend_span_funcs[SP_AN][SM_N][SC_AN][DP_AN][CPU_AVX2] = _op_blend_pan_can_dpan_avx2;
+ op_blend_span_funcs[SP][SM_N][SC_AA][DP_AN][CPU_AVX2] = _op_blend_p_caa_dpan_avx2;
+ op_blend_span_funcs[SP_AS][SM_N][SC_AA][DP_AN][CPU_AVX2] = _op_blend_pas_caa_dpan_avx2;
+ op_blend_span_funcs[SP_AN][SM_N][SC_AA][DP_AN][CPU_AVX2] = _op_blend_pan_caa_dpan_avx2;
+}
+
+#endif
diff --git a/src/lib/evas/include/evas_blend_ops.h b/src/lib/evas/include/evas_blend_ops.h
index 5bb8604ecb..1131ba758f 100644
--- a/src/lib/evas/include/evas_blend_ops.h
+++ b/src/lib/evas/include/evas_blend_ops.h
@@ -425,6 +425,8 @@ mul3_sym_sse3(__m128i x, __m128i y) {
static __m256i GA_MASK_AVX2;
static __m256i RB_MASK_AVX2;
static __m256i ALPHA_AVX2;
+static __m256i SYM4_MASK_AVX2;
+static __m256i RGB_MASK_AVX2;
#ifndef EFL_ALWAYS_INLINE
# define EFL_ALWAYS_INLINE inline
@@ -471,6 +473,135 @@ sub4_alpha_avx2(__m256i c) {
return _mm256_sub_epi32(ALPHA_AVX2, c0);
}
+/* Operation-for-operation port of mul_sym_sse3. Same lane-local reasoning as
+ * mul_256_avx2: unpacklo/unpackhi_epi16 and shuffle_ps(0x88) stay within each
+ * 128-bit half, so this is the SSE3 helper computed twice in parallel. */
+static EFL_ALWAYS_INLINE __m256i
+mul_sym_avx2(__m256i a, __m256i c) {
+
+ /* Prepare alpha for word mult */
+ __m256i a_l = a;
+ __m256i a_h = a;
+ a_l = _mm256_unpacklo_epi16(a_l, a_l);
+ a_h = _mm256_unpackhi_epi16(a_h, a_h);
+ __m256i a0 = (__m256i) _mm256_shuffle_ps( (__m256)a_l, (__m256)a_h, 0x88);
+
+ /* first part */
+ __m256i c0 = c;
+ c0 = _mm256_srli_epi32(c0, 8);
+ c0 = _mm256_and_si256(GA_MASK_AVX2, c0);
+ c0 = _mm256_mullo_epi16(a0, c0);
+ c0 = _mm256_add_epi32(c0, GA_MASK_AVX2);
+ c0 = _mm256_and_si256(RB_MASK_AVX2, c0);
+
+ /* second part */
+ __m256i c1 = c;
+ c1 = _mm256_and_si256(GA_MASK_AVX2, c1);
+ c1 = _mm256_mullo_epi16(a0, c1);
+ c1 = _mm256_add_epi32(c1, GA_MASK_AVX2);
+ c1 = _mm256_srli_epi32(c1, 8);
+ c1 = _mm256_and_si256(GA_MASK_AVX2, c1);
+
+ return _mm256_add_epi32(c0, c1);
+}
+
+/* Operation-for-operation port of mul4_sym_sse3. Lane-crossing check: on
+ * AVX2, _mm256_unpacklo_epi8(x, zero) interleaves bytes 0-7 of EACH 128-bit
+ * lane with zero (never bytes 16-23 mixing with 0-7), and unpackhi does the
+ * same for bytes 8-15 of each lane. A YMM register holds 8 DATA32 pixels, 4
+ * per 128-bit lane, so unpacklo/unpackhi split each lane's 4 pixels into its
+ * first 2 (bytes 0-7) and last 2 (bytes 8-15) - never crossing into the other
+ * lane's pixels. _mm256_packus_epi16(r_l, r_h) reassembles each lane's words
+ * back into bytes in the same low/high order per lane. So the round trip
+ * preserves per-lane element order and lane0 (pixels 0-3) never mixes with
+ * lane1 (pixels 4-7): the port is a straightforward doubling, verified
+ * against the differential test below. */
+static EFL_ALWAYS_INLINE __m256i
+mul4_sym_avx2(__m256i x, __m256i y) {
+
+ const __m256i zero = _mm256_setzero_si256();
+
+ __m256i x_l = _mm256_unpacklo_epi8(x, zero);
+ __m256i x_h = _mm256_unpackhi_epi8(x, zero);
+
+ __m256i y_l = _mm256_unpacklo_epi8(y, zero);
+ __m256i y_h = _mm256_unpackhi_epi8(y, zero);
+
+ __m256i r_l = _mm256_mullo_epi16(x_l, y_l);
+ __m256i r_h = _mm256_mullo_epi16(x_h, y_h);
+
+ r_l = _mm256_add_epi16(r_l, SYM4_MASK_AVX2);
+ r_h = _mm256_add_epi16(r_h, SYM4_MASK_AVX2);
+
+ r_l = _mm256_srli_epi16(r_l, 8);
+ r_h = _mm256_srli_epi16(r_h, 8);
+
+ return _mm256_packus_epi16(r_l, r_h);
+}
+
+static EFL_ALWAYS_INLINE __m256i
+mul3_sym_avx2(__m256i x, __m256i y) {
+
+ __m256i res = mul4_sym_avx2(x, y);
+ return _mm256_and_si256(res, RGB_MASK_AVX2);
+}
+
+/* Operation-for-operation port of interp4_256_sse3. unpacklo/unpackhi_epi8,
+ * slli_epi64/srli_epi64 (64-bit lanes, never crossing the 128-bit halves),
+ * and shuffle_ps(0x44) are all lane-local on AVX2, by the same reasoning as
+ * mul_256_avx2 and mul4_sym_avx2 above. */
+static EFL_ALWAYS_INLINE __m256i
+interp4_256_avx2(__m256i a, __m256i c0, __m256i c1)
+{
+ const __m256i zero = _mm256_setzero_si256();
+
+ __m256i a_l = a;
+ __m256i a_h = a;
+ a_l = _mm256_unpacklo_epi16(a_l, a_l);
+ a_h = _mm256_unpackhi_epi16(a_h, a_h);
+
+ __m256i a_t = _mm256_slli_epi64(a_l, 32);
+ __m256i a_t0 = _mm256_slli_epi64(a_h, 32);
+
+ a_l = _mm256_add_epi32(a_l, a_t);
+ a_h = _mm256_add_epi32(a_h, a_t0);
+
+ __m256i c0_l = c0;
+ __m256i c0_h = c0;
+
+ c0_l = _mm256_unpacklo_epi8(c0_l, zero);
+ c0_h = _mm256_unpackhi_epi8(c0_h, zero);
+
+ __m256i c1_l = c1;
+ __m256i c1_h = c1;
+
+ c1_l = _mm256_unpacklo_epi8(c1_l, zero);
+ c1_h = _mm256_unpackhi_epi8(c1_h, zero);
+
+ __m256i cl_sub = _mm256_sub_epi16(c0_l, c1_l);
+ __m256i ch_sub = _mm256_sub_epi16(c0_h, c1_h);
+
+ cl_sub = _mm256_mullo_epi16(cl_sub, a_l);
+ ch_sub = _mm256_mullo_epi16(ch_sub, a_h);
+
+ __m256i c1ls = _mm256_slli_epi16(c1_l, 8);
+ __m256i c1hs = _mm256_slli_epi16(c1_h, 8);
+
+ cl_sub = _mm256_add_epi16(cl_sub, c1ls);
+ ch_sub = _mm256_add_epi16(ch_sub, c1hs);
+
+ cl_sub = _mm256_and_si256(cl_sub, RB_MASK_AVX2);
+ ch_sub = _mm256_and_si256(ch_sub, RB_MASK_AVX2);
+
+ cl_sub = _mm256_srli_epi64(cl_sub, 8);
+ ch_sub = _mm256_srli_epi64(ch_sub, 8);
+
+ cl_sub = _mm256_packus_epi16(cl_sub, cl_sub);
+ ch_sub = _mm256_packus_epi16(ch_sub, ch_sub);
+
+ return (__m256i) _mm256_shuffle_ps( (__m256)cl_sub, (__m256)ch_sub, 0x44);
+}
+
#endif
#endif
@@ -501,23 +632,67 @@ sub4_alpha_avx2(__m256i c) {
}
/* Same shape as LOOP_ALIGNED_U1_A48 but for 256-bit kernels: scalar until DEST
- * reaches a 32-byte boundary, then 16 pixels at a time, then 8, then scalar for
- * whatever is left. DEST alignment is what lets the destination be loaded and
- * stored with the aligned intrinsics; sources stay unaligned loads. */
-#define LOOP_ALIGNED_U1_A8_A16(DEST, LENGTH, UOP, A8OP, A16OP) \
+ * reaches a 16-byte boundary, then (if needed) one 4-wide __m128i block to
+ * reach a 32-byte boundary, then 16 pixels at a time, then 8, then a 4-wide
+ * block again for a 4-7 pixel remainder, then scalar for whatever is left
+ * (1-3 pixels).
+ *
+ * The 4-wide stage exists so AVX2 and SSE3 (LOOP_ALIGNED_U1_A48) classify
+ * every pixel the same way - scalar or vector - which matters because some
+ * AVX2 helpers (mul4_sym_avx2 etc.) are wide ports of an SSE3 kernel that is
+ * a known rounding approximation relative to plain C: any pixel processed by
+ * *any* vector width (4/8/16) gets that same approximation bit-for-bit
+ * (mul4_sym_avx2 is bit-identical to mul4_sym_sse3, wide-for-wide), while a
+ * pixel processed by the scalar UOP is exact against C instead. So the two
+ * tiers are only guaranteed to agree if they draw the scalar/vector line at
+ * the same pixel.
+ *
+ * SSE3 draws that line based purely on alignment-to-16-bytes and remaining
+ * count: prologue to 16-byte alignment, then vector-process every pixel
+ * down to a less-than-4 remainder. Naively gating AVX2's *entire* prologue
+ * on 32-byte alignment (as an earlier version of this macro did) does not
+ * reproduce that: for a short, 16-but-not-32-byte-aligned span (e.g. a
+ * 4-pixel span at a 16-aligned, non-32-aligned address - an ordinary
+ * offset the differential test's length/offset sweep hits, and real render
+ * spans hit too), the 32-byte prologue would consume the *entire* span as
+ * scalar before ever reaching a vector op, while SSE3, needing only
+ * 16-byte alignment, takes its approximate 4-wide path for the same
+ * pixels - a disagreement.
+ *
+ * This macro instead: (1) aligns to 16 bytes exactly like SSE3's own
+ * prologue, so the two tiers agree pixel-for-pixel on how many leading
+ * pixels are scalar; (2) if still short of 32-byte alignment and at least 4
+ * pixels remain, runs exactly one 4-wide block to close the last 16 bytes -
+ * using the *same* arithmetic (SSE3's A4OP, when a kernel's A4OP is written
+ * that way) SSE3 would apply to those same 4 pixels regardless, so this
+ * costs nothing in exactness and satisfies _mm256_load/store_si256's 32-byte
+ * requirement for what follows; (3) proceeds with 16/8-wide blocks and a
+ * final 4-7 remainder exactly as before. Every pixel past the 16-byte-align
+ * prologue that SSE3 would vector-process, AVX2 also vector-processes
+ * (in some width - which width doesn't matter, since all of them agree
+ * bit-for-bit), and every pixel SSE3 leaves as a <4 scalar tail, AVX2 does
+ * too. */
+#define LOOP_ALIGNED_U1_A4_A8_A16(DEST, LENGTH, UOP, A4OP, A8OP, A16OP) \
{ \
- while((uintptr_t)DEST & 0x1F && LENGTH) UOP \
+ while((uintptr_t)DEST & 0xF && LENGTH) UOP \
+ \
+ if(((uintptr_t)DEST & 0x1F) && LENGTH >= 4) A4OP \
\
while(LENGTH) { \
switch(LENGTH) { \
- case 7: UOP; EINA_FALLTHROUGH; \
- case 6: UOP; EINA_FALLTHROUGH; \
- case 5: UOP; EINA_FALLTHROUGH; \
- case 4: UOP; EINA_FALLTHROUGH; \
case 3: UOP; EINA_FALLTHROUGH; \
case 2: UOP; EINA_FALLTHROUGH; \
case 1: UOP; \
break; \
+ case 7: \
+ EINA_FALLTHROUGH; \
+ case 6: \
+ EINA_FALLTHROUGH; \
+ case 5: \
+ EINA_FALLTHROUGH; \
+ case 4: \
+ A4OP \
+ break; \
case 15: \
EINA_FALLTHROUGH; \
case 14: \
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