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commit f523444e1ac4ec12975c91b307cca1767f2dbd20
Author: [email protected] <[email protected]>
AuthorDate: Mon Aug 3 21:18:29 2026 -0600
evas: EXPERIMENTAL re-enable 5 of 11 FIXME-disabled SSE3 blend slots
DO NOT MERGE UPSTREAM WITHOUT SEPARATE REVIEW. This commit is
deliberately isolated so it can be dropped or split off. It changes
SSE3 blend behaviour for every x86 user without AVX2 - a much wider
blast radius than the rest of the avx2 branch.
Eleven SSE3 blend slots across four files were left unregistered behind
"FIXME: BUGGY BUGGY Core i5 750 ..." comments dating to a 2011 bug
report (GCC 4.5.2, 32-bit Nehalem, no differential test available at
the time). We now have one (evas_test_simd_ops.c, SIMD_TIER=CPU_SSE3
vs plain C).
Ran all eleven previously-disabled slots through it:
op_blend_pixel_sse3.c [SP][SM_N][SC_N][DP_AN] PASS, bit-exact
op_blend_color_sse3.c [SP_N][SM_N][SC][DP] PASS, bit-exact
op_blend_color_sse3.c [SP_N][SM_N][SC][DP_AN] PASS, bit-exact
op_blend_mask_color_sse3.c [SP_N][SM_AS][SC][DP] PASS, bit-exact
op_blend_mask_color_sse3.c [SP_N][SM_AS][SC][DP_AN] PASS, bit-exact
op_blend_pixel_mask_sse3.c 6 slots (p/pas/pan_mas_dp[an]) FAIL - real bug,
left disabled. Kernel bodies were compiled out entirely (#if 0), not
just unregistered; the FIXME even says "most likely don't perform the
correct operation". Confirmed: SP_AS variant gave maxdelta=255 (gross
error), SP_AN variant gave maxdelta=2 with many "mismatch beyond
rounding" cases. No out-of-span writes or clobbering in either case -
the bug is purely arithmetic, not memory safety. This validates the
original 2011 report; NOT enabled here.
The five enabled here (1 in op_blend_pixel_sse3.c, 2 in
op_blend_color_sse3.c, 2 in op_blend_mask_color_sse3.c) matched the C
reference bit-for-bit (zero differing pixels, not even the usual +-1
SSE3 rounding slack) across the full evas_test_simd_ops sweep, with
zero out-of-span writes and zero source/mask clobbering.
Measured effect (buffer engine, idle machine, build-opt at -O2,
./run_expedite_avx2.sh -b build-opt -c 32 -r 5 3 4 17 75 103 58 80 21):
test sse3 before->after avx2/sse3 delta before->after
75 3.79 -> 6.61 (+74%) +190% -> +68% (Rect Blend: SC/DP, hits the
newly-enabled color slot)
17 7.27 -> 7.04 (flat) +71% -> +79% (Image Blend Unscaled: goes
through the still-disabled,
genuinely-buggy mask path,
so unaffected as expected)
103 2.55 -> 2.51 (flat) +58% -> +57%
3,4,58,80,21: unchanged within noise (unrelated/COPY/control paths)
geometric mean AVX2/SSE3 delta: +33% -> +22% (expected: SSE3 got faster)
Both gates still pass after this change:
evas_avx2_vs_sse3_ops: PASS, bit-exact. avx2-only slot count dropped
from ~11 (pixel_mask + these five) to 6 (only the still-disabled
pixel_mask slots remain avx2-only); no AVX2/SSE3 mismatch was
introduced by newly overlapping coverage.
evas_avx2_ops: PASS (tolerant gate, maxdelta=1, all inherited from sse3).
LIMITATION: this only proves the five kernels are algorithmically sound
on this machine, this compiler, this optimization level. It does not
and cannot rule out the original 2011 report, which reads like
GCC-4.5.2 32-bit Nehalem codegen fault rather than an algorithm bug -
nothing here exercises that compiler/CPU/word-size combination. Treat
this as evidence for an upstream conversation about re-enabling these
five slots, not as a unilateral all-clear.
Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>
Claude-Session: https://claude.ai/code/session_01Jvb81vpzUtFGnpoTM6npPK
---
src/lib/evas/common/evas_op_blend/op_blend_color_sse3.c | 8 ++++----
src/lib/evas/common/evas_op_blend/op_blend_mask_color_sse3.c | 8 ++++----
src/lib/evas/common/evas_op_blend/op_blend_pixel_sse3.c | 5 +++--
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_color_sse3.c b/src/lib/evas/common/evas_op_blend/op_blend_color_sse3.c
index e986f10b62..1cb02286bd 100644
--- a/src/lib/evas/common/evas_op_blend/op_blend_color_sse3.c
+++ b/src/lib/evas/common/evas_op_blend/op_blend_color_sse3.c
@@ -53,12 +53,12 @@ _op_blend_c_dp_sse3(DATA32 *s EINA_UNUSED, DATA8 *m EINA_UNUSED, DATA32 c, DATA3
static void
init_blend_color_span_funcs_sse3(void)
{
-// FIXME: BUGGY BUGGY Core i5 750 (32bit), 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4), ello (text and rectangle)
-// op_blend_span_funcs[SP_N][SM_N][SC][DP][CPU_SSE3] = _op_blend_c_dp_sse3;
+// FIXME-EXPERIMENT: re-enabled for differential testing
+ op_blend_span_funcs[SP_N][SM_N][SC][DP][CPU_SSE3] = _op_blend_c_dp_sse3;
op_blend_span_funcs[SP_N][SM_N][SC_AA][DP][CPU_SSE3] = _op_blend_caa_dp_sse3;
-// FIXME: BUGGY BUGGY Core i5 750 (32bit), 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4), ello (text and rectangle)
-// op_blend_span_funcs[SP_N][SM_N][SC][DP_AN][CPU_SSE3] = _op_blend_c_dpan_sse3;
+// FIXME-EXPERIMENT: re-enabled for differential testing
+ op_blend_span_funcs[SP_N][SM_N][SC][DP_AN][CPU_SSE3] = _op_blend_c_dpan_sse3;
op_blend_span_funcs[SP_N][SM_N][SC_AA][DP_AN][CPU_SSE3] = _op_blend_caa_dpan_sse3;
}
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_mask_color_sse3.c b/src/lib/evas/common/evas_op_blend/op_blend_mask_color_sse3.c
index 2879637157..69e277a022 100644
--- a/src/lib/evas/common/evas_op_blend/op_blend_mask_color_sse3.c
+++ b/src/lib/evas/common/evas_op_blend/op_blend_mask_color_sse3.c
@@ -168,14 +168,14 @@ _op_blend_mas_can_dp_sse3(DATA32 *s EINA_UNUSED, DATA8 *m, DATA32 c, DATA32 *d,
static void
init_blend_mask_color_span_funcs_sse3(void)
{
-// FIXME: BUGGY BUGGY Core i5 750 (32bit), 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4), ello (text and rectangle)
-// op_blend_span_funcs[SP_N][SM_AS][SC][DP][CPU_SSE3] = _op_blend_mas_c_dp_sse3;
+// FIXME-EXPERIMENT: re-enabled for differential testing
+ op_blend_span_funcs[SP_N][SM_AS][SC][DP][CPU_SSE3] = _op_blend_mas_c_dp_sse3;
op_blend_span_funcs[SP_N][SM_AS][SC_N][DP][CPU_SSE3] = _op_blend_mas_cn_dp_sse3;
op_blend_span_funcs[SP_N][SM_AS][SC_AN][DP][CPU_SSE3] = _op_blend_mas_can_dp_sse3;
op_blend_span_funcs[SP_N][SM_AS][SC_AA][DP][CPU_SSE3] = _op_blend_mas_caa_dp_sse3;
-// FIXME: BUGGY BUGGY Core i5 2500 (64bit), gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4), ello (text)
-// op_blend_span_funcs[SP_N][SM_AS][SC][DP_AN][CPU_SSE3] = _op_blend_mas_c_dpan_sse3;
+// FIXME-EXPERIMENT: re-enabled for differential testing
+ op_blend_span_funcs[SP_N][SM_AS][SC][DP_AN][CPU_SSE3] = _op_blend_mas_c_dpan_sse3;
op_blend_span_funcs[SP_N][SM_AS][SC_N][DP_AN][CPU_SSE3] = _op_blend_mas_cn_dpan_sse3;
op_blend_span_funcs[SP_N][SM_AS][SC_AN][DP_AN][CPU_SSE3] = _op_blend_mas_can_dpan_sse3;
op_blend_span_funcs[SP_N][SM_AS][SC_AA][DP_AN][CPU_SSE3] = _op_blend_mas_caa_dpan_sse3;
diff --git a/src/lib/evas/common/evas_op_blend/op_blend_pixel_sse3.c b/src/lib/evas/common/evas_op_blend/op_blend_pixel_sse3.c
index 76ef880d44..b76ab36d33 100644
--- a/src/lib/evas/common/evas_op_blend/op_blend_pixel_sse3.c
+++ b/src/lib/evas/common/evas_op_blend/op_blend_pixel_sse3.c
@@ -146,8 +146,9 @@ init_blend_pixel_span_funcs_sse3(void)
op_blend_span_funcs[SP_AS][SM_N][SC_N][DP][CPU_SSE3] = _op_blend_pas_dp_sse3;
op_blend_span_funcs[SP_AN][SM_N][SC_N][DP][CPU_SSE3] = _op_blend_pan_dp_sse3;
-// FIXME: BUGGY BUGGY Core i5 750 (32bit), 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4), ello (text and rectangle)
-// op_blend_span_funcs[SP][SM_N][SC_N][DP_AN][CPU_SSE3] = _op_blend_p_dpan_sse3;
+// FIXME-EXPERIMENT: re-enabled for differential testing, see
+// .superpowers/sdd/2026-08-03-evas-avx2-blend-ops/sse3-fixme-investigation.md
+ op_blend_span_funcs[SP][SM_N][SC_N][DP_AN][CPU_SSE3] = _op_blend_p_dpan_sse3;
op_blend_span_funcs[SP_AS][SM_N][SC_N][DP_AN][CPU_SSE3] = _op_blend_pas_dpan_sse3;
op_blend_span_funcs[SP_AN][SM_N][SC_N][DP_AN][CPU_SSE3] = _op_blend_pan_dpan_sse3;
}
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