Lars Andersson wrote:
>
>> Jon Elson wrote:
>> except that the extended control reg. to set it to EPP mode was at a
>> different address than the customary base address + 0x402.
>>
> I would be interested in what actual address you found.
>
The unit I have is labeled on the board :
Siig 2020 / CyberPro V6.0
It uses the Oxford OX9162 chip, and
Shows up with lspci -v as :
EC00 (8 bytes)
E880 (4 bytes)
E800 (32 bytes)
EC00 is the par port base address
The LinuxCNC ppmc driver correctly handles the offset to the
ECR address, so no special attention is needed. I think the
Mesa drivers also would handle it right, it is marked in the
pnp data block by the pci enumeration BIOS code.
My very unsophisticated diagnositcs program doesn't know how
to read this data, so it has to be set up with the pcisetup
program, which blindly writes 0x80 to the I/O port 0x402
higher than the address it is given in the command line.
On completely standard parallel ports, the data register is at
0x378, the ECR is at 0x77A (378 + 402 in hex).
To use ppmcdiags, run pcisetup E480, as
apparently E880 is the control reg block.
These addresses may change depending on what is in other
PCI slots, so look for the block of 4 registers, that should
be the config regs block, and the 3rd one would be the
ECR. The block of 8 regs would start with the data
port. I don't know what the block of 32 regs does.
Jon
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