>
> If I have the EPP mode set to 1.7, I can load SV8B.BIT into the board, add
> read and write components to the threads, and start the RT Kernel now.
Looking at the EPP interface in the FPGA and the CPLD, the CPLD (loader)
should work with EPP V1.7 or EPP V1.9 but the FPGA code will definately fail
with EPP V1.7 if a new strobe is asserted before wait has gone low again from
a previous cycle. The FPGA code is deliberately slower so that it can ignore
signals of less than about 300 nS duration, this requires EPP V1.9. I'll do
some testing on Monday, but this suggests that possibly your BIOS has the EPP
modes names reversed.
>
> (Sebastian - the suggestion to go from 100,000 ns timing to 1,000,000 ns
> timing was effective, thank you - lockups gone)
>
> However, no response to external stimulus (I have a confirmed good encoder
> attached to encoder 01 input, have moved from active hi/active low configs,
> no change.)
>
>
>
> If I change BIOS to EPP 1.9, hm2_7i43 components will fail to load, halrun
> notes:
>
> Error inserting '/home/cnc/emc2-trunk/rtlib/hm2_7i43.ko': -1 Input/output
> error
>
>
>
> And dmesg output indicates:
>
> [timing..] Hm2/hm2_7i43.0: error reading HM2 Config name
>
> [more timing.] hm2_7i43.0: board at (ioaddr=0x0378, ioaddr_hi=0x0778,
> epp_wide ON) not found!
>
>
>
> Adding the epp_wide=0 token doesn't affect the outcome (although it does
> accept and indicate epp_wide OFF during the resulting dmesg).
>
>
>
> /lib/firmware folder is populated, symlinked and does have the requested
> .BIT files inside it.
>
>
>
> I've noted in other posts that it's the 200K board currently being worked
> on..do I need to downgrade for this to get going? Using the "..S.BIT"
> firmwares obviously fails (dmesg says "bad token"), substituting the other
> ".B.BIT" firmwares results in the same failures as "SV8B.BIT".
>
>
>
> I have tried this on 2 separate motherboards (my Epia M10000 and a GeForce
> 6100) with same results, as well as a PCI parallel port card (which was a
> total disaster). I don't think it's a MB/Bios issue.
>
>
>
> Cable between the LPT port and the 7i43 is a freshly-crimped 12" ribbon
> cable, replaced with repeatable results.
>
>
>
> Kindest regards,
>
>
>
> Ted.
>
>
>
>
>
>
Peter Wallace
Mesa Electronics
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