On Thu, 2018-12-27 at 15:26 -0800, Jim Wilson wrote: > Started with the aarch64 support and modified it for RISC-V. The > flattened > structure support hasn't been written yet, but the rest of it should > be > correct for the LP64D ABI. We have potentially 6 different ABIs to > support, > so this requires checking elf header flags in riscv_init when setting > the hook.
nitpick. Please keep the commit message lines < 76 chars if possible. Looks good and it resolves the run-native-test.sh (on risc-v). We really should add a non-native test, so it is easier to test on other arches. But currently only aarch64 has one (run-funcretval.sh). I'll see if I can extend that to other arches. Then we can also see if we can get the aggregates correct. The comments explain things well, but it would be good to have official references to the calling convention and DWARF register mappings. The calling convention is explained in: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#procedure-calling-convention But I couldn't find an official DWARF register mapping. If you have references I like to add them to the code. Pushed as is. Thanks, Mark BTW. Just for other reviewers. > +static int > +pass_in_gpr_lp64 (const Dwarf_Op **locp, Dwarf_Word size) > +{ > + static const Dwarf_Op loc[] = > + { > + { .atom = DW_OP_reg10 }, { .atom = DW_OP_piece, .number = 8 }, > + { .atom = DW_OP_reg11 }, { .atom = DW_OP_piece, .number = 8 } > + }; > + > + *locp = loc; > + return size <= 8 ? 1 : 4; > +} Other backends also do this, but it might not be immediately clear (at least I had to double check). When the size fits into a register we pretend that the returned loc description is simply of size 1 (DW_OP_reg10), otherwise it is split across the two registers (size 4, two pieces).
