This conflicts with the previoues two patches. Adds 32-bit support exactly the
same way that the sparc backend handles 32- and 64-bit core file support. The
64-bit core file support was tested and still works same as before.
Signed-off-by: Jim Wilson <j...@sifive.com>
---
backends/ChangeLog | 11 +++++++++
backends/Makefile.am | 2 +-
backends/riscv64_corenote.c | 2 ++
backends/riscv_corenote.c | 45 +++++++++++++++++++++++++++----------
backends/riscv_init.c | 7 +++++-
5 files changed, 53 insertions(+), 14 deletions(-)
create mode 100644 backends/riscv64_corenote.c
diff --git a/backends/ChangeLog b/backends/ChangeLog
index 637aa8c2..58a1b775 100644
--- a/backends/ChangeLog
+++ b/backends/ChangeLog
@@ -1,5 +1,16 @@
2018-12-27 Jim Wilson <j...@sifive.com>
+ * Makefile.am (riscv_SRCS): Add riscv64_corenote.c.
+ * riscv64_corenote.c: New file.
+ * riscv_corenote.c (BITS): New.
+ (BACKEND): Conditional on BITS.
+ (ULONG, UID_T, GID_T, ALIGN_ULONG, ALIGN_UID_T, ALIGN_GID_T): Likewise.
+ (TYPE_ULONG, TYPE_UID_T, TYPE_GID_T): Likewise.
+ (prstatus_regs): Use BITS/8 instead of 8.
+ (PRSTATUS_REGS_SIZE): Likewise.
+ * riscv_init.c (riscv64_core_note): Declare.
+ (riscv_init): If ELFCLASS64 then use riscv64_core_note hook.
+
* Makefile.am (riscv_SRCS): Add riscv_retval.c.
* riscv_init.c: Include libelfP.h.
(riscv_return_value_location_lp64d): Declare.
diff --git a/backends/Makefile.am b/backends/Makefile.am
index fedeb93a..2126a2ec 100644
--- a/backends/Makefile.am
+++ b/backends/Makefile.am
@@ -132,7 +132,7 @@ libebl_bpf_pic_a_SOURCES = $(bpf_SRCS)
am_libebl_bpf_pic_a_OBJECTS = $(bpf_SRCS:.c=.os)
riscv_SRCS = riscv_init.c riscv_symbol.c riscv_cfi.c riscv_regs.c \
- riscv_initreg.c riscv_corenote.c riscv_retval.c
+ riscv_initreg.c riscv_corenote.c riscv64_corenote.c riscv_retval.c
libebl_riscv_pic_a_SOURCES = $(riscv_SRCS)
am_libebl_riscv_pic_a_OBJECTS = $(riscv_SRCS:.c=.os)
diff --git a/backends/riscv64_corenote.c b/backends/riscv64_corenote.c
new file mode 100644
index 00000000..dbcb89d9
--- /dev/null
+++ b/backends/riscv64_corenote.c
@@ -0,0 +1,2 @@
+#define BITS 64
+#include "riscv_corenote.c"
diff --git a/backends/riscv_corenote.c b/backends/riscv_corenote.c
index afb84bee..b728903f 100644
--- a/backends/riscv_corenote.c
+++ b/backends/riscv_corenote.c
@@ -35,27 +35,48 @@
#include <stdio.h>
#include <sys/time.h>
-#define BACKEND riscv_
+#ifndef BITS
+# define BITS 32
+# define BACKEND riscv_
+#else
+# define BITS 64
+# define BACKEND riscv64_
+#endif
+
#include "libebl_CPU.h"
-#define ULONG uint64_t
+#if BITS == 32
+# define ULONG uint32_t
+# define UID_T uint16_t
+# define GID_T uint16_t
+# define ALIGN_ULONG 4
+# define ALIGN_UID_T 2
+# define ALIGN_GID_T 2
+# define TYPE_ULONG ELF_T_WORD
+# define TYPE_UID_T ELF_T_HALF
+# define TYPE_GID_T ELF_T_HALF
+#else
+# define ULONG uint64_t
+# define UID_T uint32_t
+# define GID_T uint32_t
+# define ALIGN_ULONG 8
+# define ALIGN_UID_T 4
+# define ALIGN_GID_T 4
+# define TYPE_ULONG ELF_T_XWORD
+# define TYPE_UID_T ELF_T_WORD
+# define TYPE_GID_T ELF_T_WORD
+#endif
+
#define PID_T int32_t
-#define UID_T uint32_t
-#define GID_T uint32_t
-#define ALIGN_ULONG 8
#define ALIGN_PID_T 4
-#define ALIGN_UID_T 4
-#define ALIGN_GID_T 4
-#define TYPE_ULONG ELF_T_XWORD
#define TYPE_PID_T ELF_T_SWORD
-#define TYPE_UID_T ELF_T_WORD
-#define TYPE_GID_T ELF_T_WORD
+
static const Ebl_Register_Location prstatus_regs[] =
{
- { .offset = 8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
+ { .offset = BITS/8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
};
-#define PRSTATUS_REGS_SIZE (32 * 8)
+#define PRSTATUS_REGS_SIZE (32 * (BITS/8))
#define PRSTATUS_REGSET_ITEMS \
{ \
diff --git a/backends/riscv_init.c b/backends/riscv_init.c
index ecee2910..3398c104 100644
--- a/backends/riscv_init.c
+++ b/backends/riscv_init.c
@@ -41,6 +41,8 @@
extern __typeof (EBLHOOK (return_value_location))
riscv_return_value_location_lp64d attribute_hidden;
+extern __typeof (EBLHOOK (core_note)) riscv64_core_note attribute_hidden;
+
const char *
riscv_init (Elf *elf,
GElf_Half machine __attribute__ ((unused)),
@@ -62,7 +64,10 @@ riscv_init (Elf *elf,
HOOK (eh, check_special_symbol);
HOOK (eh, machine_flag_check);
HOOK (eh, set_initial_registers_tid);
- HOOK (eh, core_note);
+ if (eh->class == ELFCLASS64)
+ eh->core_note = riscv64_core_note;
+ else
+ HOOK (eh, core_note);
if (eh->class == ELFCLASS64
&& ((elf->state.elf64.ehdr->e_flags & EF_RISCV_FLOAT_ABI)
== EF_RISCV_FLOAT_ABI_DOUBLE))
--
2.19.2
