Branch: refs/heads/angushe/riscv-symtab-api
Home: https://github.com/dyninst/dyninst
Commit: f13154269f286a3565d12e32c0806b9cbf2f3fe3
https://github.com/dyninst/dyninst/commit/f13154269f286a3565d12e32c0806b9cbf2f3fe3
Author: wxrdnx <wxr...@protonmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M common/CMakeLists.txt
M common/h/Architecture.h
M common/h/dyn_regs.h
M common/h/entryIDs.h
A common/h/mnemonics/riscv64_entryIDs.h
A common/h/registers/riscv64_regs.h
M common/src/registers/MachRegister.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M dwarf/src/dwarfHandle.C
M dwarf/src/registers/convert.C
A dwarf/src/registers/riscv64.h
M elf/src/Elf_X.C
A external/rose/riscv64InstructionEnum.h
M instructionAPI/capstone/import_mnemonics.py
A instructionAPI/capstone/riscv64/mnemonics.py
A instructionAPI/capstone/riscv64/registers.py
M instructionAPI/src/Instruction.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/src/SymbolicExpression.C
M proccontrol/src/process.C
Log Message:
-----------
Add RISC-V instruction mnemonics and registers
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