Hi Heiko,
On Fri, 2020-04-03 at 13:15 -0300, Helen Koike wrote:
> From: Shunqian Zheng <zhen...@rock-chips.com>
>
> Designware MIPI D-PHY, used for ISP0 in rk3399.
>
> Verified with:
> make ARCH=arm64 dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml
>
> Signed-off-by: Shunqian Zheng <zhen...@rock-chips.com>
> Signed-off-by: Jacob Chen <jacob2.c...@rock-chips.com>
> Signed-off-by: Helen Koike <helen.ko...@collabora.com>
>
> ---
>
> Changes in v2:
> - fix alignment of clocks
>
> V1:
> This patchset came from the original ISP series from Rockchip:
>
> https://patchwork.kernel.org/patch/10267409/
>
Can you take the devicetree changes (patches 8 and 9) ?
Thanks,
Ezequiel
> The only difference is:
> - add phy-cells
> - update compatible to "rockchip,rk3399-mipi-dphy-rx0"
> - commit message
> ---
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 33cc21fcf4c10..6b3380b10e596 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1394,6 +1394,17 @@ io_domains: io-domains {
> status = "disabled";
> };
>
> + mipi_dphy_rx0: mipi-dphy-rx0 {
> + compatible = "rockchip,rk3399-mipi-dphy-rx0";
> + clocks = <&cru SCLK_MIPIDPHY_REF>,
> + <&cru SCLK_DPHY_RX0_CFG>,
> + <&cru PCLK_VIO_GRF>;
> + clock-names = "dphy-ref", "dphy-cfg", "grf";
> + power-domains = <&power RK3399_PD_VIO>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> u2phy0: usb2-phy@e450 {
> compatible = "rockchip,rk3399-usb2phy";
> reg = <0xe450 0x10>;
> --
> 2.26.0
>
>
_______________________________________________
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
