> > From: Dean Luick <dean.lu...@intel.com>
> >
> > Correctly reduce the number of VLs when limited by the number of SDMA
> > engines.
> 
> why?  What does this "solve"?

The hardware has multiple egress mechanisms, SDMA and pio, and multiples of 
those.

These mechanisms are chosen using the VL (8)

The fix corrects a panic issue with one of the platforms that doesn't have 
enough SDMA (4) mechanisms for the typical number of VLs.

Mike

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