On 09/10/15 19:34, H Hartley Sweeten wrote:
As suggested by checkpatch.pl, use the BIT macro to define the
register bits.

Signed-off-by: H Hartley Sweeten <hswee...@visionengravers.com>
Cc: Ian Abbott <abbo...@mev.co.uk>
Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org>
---
  drivers/staging/comedi/drivers/adl_pci9111.c | 41 ++++++++++++++--------------
  1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/drivers/staging/comedi/drivers/adl_pci9111.c 
b/drivers/staging/comedi/drivers/adl_pci9111.c
index c9df3af..dd42bd0a 100644
--- a/drivers/staging/comedi/drivers/adl_pci9111.c
+++ b/drivers/staging/comedi/drivers/adl_pci9111.c
@@ -89,23 +89,24 @@ TODO:
  #define PCI9111_EDIO_REG              0x04
  #define PCI9111_AI_CHANNEL_REG                0x06
  #define PCI9111_AI_RANGE_STAT_REG     0x08
-#define PCI9111_AI_STAT_AD_BUSY                (1 << 7)
-#define PCI9111_AI_STAT_FF_FF          (1 << 6)
-#define PCI9111_AI_STAT_FF_HF          (1 << 5)
-#define PCI9111_AI_STAT_FF_EF          (1 << 4)
-#define PCI9111_AI_RANGE_MASK          (7 << 0)
+#define PCI9111_AI_STAT_AD_BUSY                BIT(7)
+#define PCI9111_AI_STAT_FF_FF          BIT(6)
+#define PCI9111_AI_STAT_FF_HF          BIT(5)
+#define PCI9111_AI_STAT_FF_EF          BIT(4)
+#define PCI9111_AI_RANGE(x)            (((x) & 0x7) << 0)
+#define PCI9111_AI_RANGE_MASK          PCI9111_AI_RANGE(7)
  #define PCI9111_AI_TRIG_CTRL_REG      0x0a
-#define PCI9111_AI_TRIG_CTRL_TRGEVENT  (1 << 5)
-#define PCI9111_AI_TRIG_CTRL_POTRG     (1 << 4)
-#define PCI9111_AI_TRIG_CTRL_PTRG      (1 << 3)
-#define PCI9111_AI_TRIG_CTRL_ETIS      (1 << 2)
-#define PCI9111_AI_TRIG_CTRL_TPST      (1 << 1)
-#define PCI9111_AI_TRIG_CTRL_ASCAN     (1 << 0)
+#define PCI9111_AI_TRIG_CTRL_TRGEVENT  BIT(5)
+#define PCI9111_AI_TRIG_CTRL_POTRG     BIT(4)
+#define PCI9111_AI_TRIG_CTRL_PTRG      BIT(3)
+#define PCI9111_AI_TRIG_CTRL_ETIS      BIT(2)
+#define PCI9111_AI_TRIG_CTRL_TPST      BIT(1)
+#define PCI9111_AI_TRIG_CTRL_ASCAN     BIT(0)
  #define PCI9111_INT_CTRL_REG          0x0c
-#define PCI9111_INT_CTRL_ISC2          (1 << 3)
-#define PCI9111_INT_CTRL_FFEN          (1 << 2)
-#define PCI9111_INT_CTRL_ISC1          (1 << 1)
-#define PCI9111_INT_CTRL_ISC0          (1 << 0)
+#define PCI9111_INT_CTRL_ISC2          BIT(3)
+#define PCI9111_INT_CTRL_FFEN          BIT(2)
+#define PCI9111_INT_CTRL_ISC1          BIT(1)
+#define PCI9111_INT_CTRL_ISC0          BIT(0)
  #define PCI9111_SOFT_TRIG_REG         0x0e
  #define PCI9111_8254_BASE_REG         0x40
  #define PCI9111_INT_CLR_REG           0x48

Okay, but,,,

@@ -363,6 +364,7 @@ static int pci9111_ai_do_cmd(struct comedi_device *dev,
        struct pci9111_private_data *dev_private = dev->private;
        struct comedi_cmd *cmd = &s->async->cmd;
        unsigned int last_chan = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
+       unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
        unsigned int trig = 0;

        /*  Set channel scan limit */
@@ -374,11 +376,8 @@ static int pci9111_ai_do_cmd(struct comedi_device *dev,

        outb(last_chan, dev->iobase + PCI9111_AI_CHANNEL_REG);

-       /*  Set gain */
-       /*  This is the same gain on every channel */
-
-       outb(CR_RANGE(cmd->chanlist[0]) & PCI9111_AI_RANGE_MASK,
-            dev->iobase + PCI9111_AI_RANGE_STAT_REG);
+       /*  Set gain - all channels use the same range */
+       outb(PCI9111_AI_RANGE(range0), dev->iobase + PCI9111_AI_RANGE_STAT_REG);

        /*  Set timer pacer */
        dev_private->scan_delay = 0;
@@ -571,7 +570,7 @@ static int pci9111_ai_insn_read(struct comedi_device *dev,

        status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
        if ((status & PCI9111_AI_RANGE_MASK) != range) {
-               outb(range & PCI9111_AI_RANGE_MASK,
+               outb(PCI9111_AI_RANGE(range),
                     dev->iobase + PCI9111_AI_RANGE_STAT_REG);
        }



Shouldn't that stuff be in a separate patch?

--
-=( Ian Abbott @ MEV Ltd.    E-mail: <abbo...@mev.co.uk> )=-
-=(                          Web: http://www.mev.co.uk/  )=-
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