If the hypervisor supports MSR based access to the APIC registers
(EOI, TPR and ICR), implement the MSR based access.

Signed-off-by: K. Y. Srinivasan <k...@microsoft.com>
---
 Changes from V1: Addressed comments from Ingo Molnar 
<mingo.kernel....@gmail.com>

 arch/x86/kernel/cpu/mshyperv.c |   62 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 62 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 939155f..76833c6 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -110,6 +110,57 @@ static struct clocksource hyperv_cs = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static u64 ms_hv_apic_icr_read(void)
+{
+       u64 reg_val;
+
+       rdmsrl(HV_X64_MSR_ICR, reg_val);
+       return reg_val;
+}
+
+static void ms_hv_apic_icr_write(u32 low, u32 id)
+{
+       u64 reg_val;
+
+       reg_val = SET_APIC_DEST_FIELD(id);
+       reg_val = reg_val << 32;
+       reg_val |= low;
+
+       wrmsrl(HV_X64_MSR_ICR, reg_val);
+}
+
+static u32 ms_hv_apic_read(u32 reg)
+{
+       u32 reg_val, hi;
+
+       switch (reg) {
+       case APIC_EOI:
+               rdmsr(HV_X64_MSR_EOI, reg_val, hi);
+               return reg_val;
+       case APIC_TASKPRI:
+               rdmsr(HV_X64_MSR_TPR, reg_val, hi);
+               return reg_val;
+
+       default:
+               return native_apic_mem_read(reg);
+       }
+}
+
+static void ms_hv_apic_write(u32 reg, u32 val)
+{
+       switch (reg) {
+       case APIC_EOI:
+               wrmsr(HV_X64_MSR_EOI, val, 0);
+               break;
+       case APIC_TASKPRI:
+               wrmsr(HV_X64_MSR_TPR, val, 0);
+               break;
+       default:
+               native_apic_mem_write(reg, val);
+       }
+}
+
+
 static void __init ms_hyperv_init_platform(void)
 {
        /*
@@ -143,6 +194,17 @@ static void __init ms_hyperv_init_platform(void)
        no_timer_check = 1;
 #endif
 
+       if (ms_hyperv.features & HV_X64_MSR_APIC_ACCESS_AVAILABLE) {
+               /*
+                * Setup the hooks for optimized APIC read/write.
+                */
+               apic->read      = ms_hv_apic_read;
+               apic->write     = ms_hv_apic_write;
+               apic->icr_write = ms_hv_apic_icr_write;
+               apic->icr_read  = ms_hv_apic_icr_read;
+               apic->eoi_write = ms_hv_apic_write;
+       }
+
 }
 
 const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
-- 
1.7.4.1

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