Daniel Vetter <daniel at ffwll.ch> writes: > Matching tiling modes is actually already a requirement on gen4+ (since > the tiling bit and the linear/tiled offset registers can't be changed with > a MI_DISPLAY_FLIP command).
Async flip has a harder requirement -- you must use X tiling, both before and after the flip. Oh, and async flips require a 32KB aligned buffer, which I'm not actually checking for. Not sure how to > But atm we fail to check that in the common > code, so imo better to move that to there. > > We already check for matching strides in common code, so with the tile > check added we could drop this all here. I don't see a requirement for matching stride and tile parameter in the MI_DISPLAY_FLIP docs for synchronous operations, at least on DevGT+. Is the common code too restrictive? -- keith.packard at intel.com -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 827 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130724/ac67786f/attachment.pgp>
