[PATCH 1/2] drm/exynos: consider common clock framework to g2d driver.

[Inki Dae]

This patch just changes clk_enable/disable to
clk_prepare_enable/clk_disable_unprepare, and
adds related exception codes.

Signed-off-by: Inki Dae <inki.dae at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/gpu/drm/exynos/exynos_drm_g2d.c |   17 ++++++++++++++---
 1 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c 
b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 4722662..f81cfd4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -806,9 +806,20 @@ static void g2d_dma_start(struct g2d_data *g2d,
        struct g2d_cmdlist_node *node =
                                list_first_entry(&runqueue_node->run_cmdlist,
                                                struct g2d_cmdlist_node, list);
+       int ret;
+
+       ret = pm_runtime_get_sync(g2d->dev);
+       if (ret < 0) {
+               dev_warn(g2d->dev, "failed pm power on.\n");
+               return;
+       }

-       pm_runtime_get_sync(g2d->dev);
-       clk_enable(g2d->gate_clk);
+       ret = clk_prepare_enable(g2d->gate_clk);
+       if (ret < 0) {
+               dev_warn(g2d->dev, "failed to enable clock.\n");
+               pm_runtime_put_sync(g2d->dev);
+               return;
+       }

        writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
        writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
@@ -861,7 +872,7 @@ static void g2d_runqueue_worker(struct work_struct *work)
                                            runqueue_work);

        mutex_lock(&g2d->runqueue_mutex);
-       clk_disable(g2d->gate_clk);
+       clk_disable_unprepare(g2d->gate_clk);
        pm_runtime_put_sync(g2d->dev);

        complete(&g2d->runqueue_node->complete);
-- 
1.7.5.4