Am 11.04.2013 00:20, schrieb j.glisse at gmail.com:
> From: Jerome Glisse <jglisse at redhat.com>
>
> v2: sync with radeon-next tree for 3.10
>
> http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip
>
> Signed-off-by: Jerome Glisse <jglisse at redhat.com>
Reviewed-by: Christian K?nig <christian.koenig at amd.com>
> ---
> include/drm/radeon_drm.h | 81
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
> index 00d66b3..86cef15 100644
> --- a/include/drm/radeon_drm.h
> +++ b/include/drm/radeon_drm.h
> @@ -509,6 +509,7 @@ typedef struct {
> #define DRM_RADEON_GEM_SET_TILING 0x28
> #define DRM_RADEON_GEM_GET_TILING 0x29
> #define DRM_RADEON_GEM_BUSY 0x2a
> +#define DRM_RADEON_GEM_VA 0x2b
>
> #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE +
> DRM_RADEON_CP_INIT, drm_radeon_init_t)
> #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE +
> DRM_RADEON_CP_START)
> @@ -550,6 +551,7 @@ typedef struct {
> #define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE +
> DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
> #define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE +
> DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
> #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE +
> DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
> +#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE +
> DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
>
> typedef struct drm_radeon_init {
> enum {
> @@ -882,8 +884,43 @@ struct drm_radeon_gem_pwrite {
> uint64_t data_ptr;
> };
>
> +#define RADEON_VA_MAP 1
> +#define RADEON_VA_UNMAP 2
> +
> +#define RADEON_VA_RESULT_OK 0
> +#define RADEON_VA_RESULT_ERROR 1
> +#define RADEON_VA_RESULT_VA_EXIST 2
> +
> +#define RADEON_VM_PAGE_VALID (1 << 0)
> +#define RADEON_VM_PAGE_READABLE (1 << 1)
> +#define RADEON_VM_PAGE_WRITEABLE (1 << 2)
> +#define RADEON_VM_PAGE_SYSTEM (1 << 3)
> +#define RADEON_VM_PAGE_SNOOPED (1 << 4)
> +
> +struct drm_radeon_gem_va {
> + uint32_t handle;
> + uint32_t operation;
> + uint32_t vm_id;
> + uint32_t flags;
> + uint64_t offset;
> +};
> +
> #define RADEON_CHUNK_ID_RELOCS 0x01
> #define RADEON_CHUNK_ID_IB 0x02
> +#define RADEON_CHUNK_ID_FLAGS 0x03
> +#define RADEON_CHUNK_ID_CONST_IB 0x04
> +
> +/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
> +#define RADEON_CS_KEEP_TILING_FLAGS 0x01
> +#define RADEON_CS_USE_VM 0x02
> +#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS
> is the last one */
> +/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring
> type */
> +#define RADEON_CS_RING_GFX 0
> +#define RADEON_CS_RING_COMPUTE 1
> +#define RADEON_CS_RING_DMA 2
> +#define RADEON_CS_RING_UVD 3
> +/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the
> priority */
> +/* 0 = normal, + = higher priority, - = lower priority */
>
> struct drm_radeon_cs_chunk {
> uint32_t chunk_id;
> @@ -891,6 +928,8 @@ struct drm_radeon_cs_chunk {
> uint64_t chunk_data;
> };
>
> +/* drm_radeon_cs_reloc.flags */
> +
> struct drm_radeon_cs_reloc {
> uint32_t handle;
> uint32_t read_domains;
> @@ -916,6 +955,30 @@ struct drm_radeon_cs {
> #define RADEON_INFO_ACCEL_WORKING2 0x05
> #define RADEON_INFO_TILING_CONFIG 0x06
> #define RADEON_INFO_WANT_HYPERZ 0x07
> +#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on
> r300 */
> +#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency
> */
> +#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need
> for OQ */
> +#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
> +#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT
> were broken before this */
> +#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map,
> needed by mesa */
> +/* virtual address start, va < start are reserved by the kernel */
> +#define RADEON_INFO_VA_START 0x0e
> +/* maximum size of ib using the virtual memory cs */
> +#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
> +/* max pipes - needed for compute shaders */
> +#define RADEON_INFO_MAX_PIPES 0x10
> +/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock
> */
> +#define RADEON_INFO_TIMESTAMP 0x11
> +/* max shader engines (SE) - needed for geometry shaders, etc. */
> +#define RADEON_INFO_MAX_SE 0x12
> +/* max SH per SE */
> +#define RADEON_INFO_MAX_SH_PER_SE 0x13
> +/* fast fb access is enabled */
> +#define RADEON_INFO_FASTFB_WORKING 0x14
> +/* query if a RADEON_CS_RING_* submission is supported */
> +#define RADEON_INFO_RING_WORKING 0x15
> +/* SI tile mode array */
> +#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
>
> struct drm_radeon_info {
> uint32_t request;
> @@ -923,4 +986,22 @@ struct drm_radeon_info {
> uint64_t value;
> };
>
> +/* Those correspond to the tile index to use, this is to explicitly state
> + * the API that is implicitly defined by the tile mode array.
> + */
> +#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
> +#define SI_TILE_MODE_COLOR_1D 13
> +#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
> +#define SI_TILE_MODE_COLOR_2D_8BPP 14
> +#define SI_TILE_MODE_COLOR_2D_16BPP 15
> +#define SI_TILE_MODE_COLOR_2D_32BPP 16
> +#define SI_TILE_MODE_COLOR_2D_64BPP 17
> +#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
> +#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
> +#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
> +#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
> +#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
> +#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
> +#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
> +
> #endif
