On 11/2/26 22:28, Martin Blumenstingl wrote:
There's a report from a user with a DELL U3415W monitor and a Khadas VIM3 stating that 3440x1440@50Hz works but 3440x1440@60Hz doesn't. edid-decode Detailed Timing Descriptor (DTD) extract of that mode: DTD 1: 3440x1440 59.972616 Hz 43:18 88.819 kHz 319.750000 MHz Hfront 80 Hsync 32 Hback 48 Hpol P Vfront 28 Vsync 10 Vback 3 Vpol NThose high clock rates are currently not supported by the meson_vclk code as it limits the PLL OD (output divider) to a minimum of 2. The formula to calculate the clock internally is (ignoring fractional dividers): 319.750MHz * 10 * od = 24MHz * m With od = 2 this results in m = 266, which is outside the supported range of the PLL on G12A SoCs (the driver limits m to 106..247). Using od = 2 results in m = 133, which is supported. Allow the driver to pick OD = 1 to gain support for modes such as 3440x1440@60Hz. Link: https://forum.khadas.com/t/can-not-set-display-resolution-to-3440x1440-for-dell-monitor/26271/12 Signed-off-by: Martin Blumenstingl <[email protected]> --- Re-send of [0] which seems to have slipped through. [0] https://lore.kernel.org/linux-amlogic/[email protected]/ drivers/gpu/drm/meson/meson_vclk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index dfe0c28a0f05..c0be0b7655bf 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -700,8 +700,8 @@ static bool meson_hdmi_pll_find_params(struct meson_drm *priv, unsigned int *frac, unsigned int *od) { - /* Cycle from /16 to /2 */ - for (*od = 16 ; *od > 1 ; *od >>= 1) { + /* Cycle from /16 to /1 */ + for (*od = 16 ; *od > 0 ; *od >>= 1) { *m = meson_hdmi_pll_get_m(priv, freq * *od); if (!*m) continue; @@ -750,7 +750,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, /* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */ od3 = 1; if (od < 4) { - od1 = 2; + od1 = od; od2 = 1; } else { od2 = od / 4;
Reviewed-by: Neil Armstrong <[email protected]> Thanks, Neil
