On 10/29/26 2:52 PM, Anna Maniscalco wrote: > Program all the register needed to start up LPAC and send initialization > sequence. > > Additionally, now that the LPAC ring is live, make the code aware of it. > > Signed-off-by: Anna Maniscalco <[email protected]> > ---
[...] > + /* *Don't* send a power up reg list for concurrent binning (TODO) */ Here's what my robot came up with human tldr: missing the listed registers from a750_ifpc_reglist_regs[] and a7xx_pwrup_reglist_regs[] LLM: The strongest IFPC-specific suspect is that LPAC setup is not fully restored after IFPC. The series enables LPAC on gen70900 (Adreno 750), which already has ADRENO_QUIRK_IFPC. When LPAC is active, patch 09 programs several GX registers in hw_init(), but adds only CP_LPAC_PROTECT_CNTL to the A750 IFPC restore list. The missing registers are: - UCHE_DEBUG_CNTL_1 (bit 30) - CP_LPAC_CHICKEN_DBG - SP_CHICKEN_BITS_2 - SP_LPAC_CHICKEN_BITS_2 A likely fix is to include those LPAC registers in the A750 IFPC restore list and the applicable general power-up list, so their initialized values survive collapse. The KGSL code in this checkout has a similar pattern: it conditionally adds LPAC chicken-bit registers to the Gen7 IFPC list when LPAC is enabled (adreno_gen7.c:652–660). Konrad
