From: Ishu Brar <[email protected]> The A690 entry carries a list of the Bus Clock Managers it votes for (SH0, MC0 and ACV) which is the same for other A6xx GPUs. Move it to a shared array so that more entries can refer to it instead of repeating it.
No functional change. Assisted-by: Claude Signed-off-by: Ishu Brar <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 4ef2bd6e7..c4d332f48 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -736,6 +736,17 @@ static const struct adreno_reglist a702_hwcg[] = { {} }; +static const struct a6xx_bcm a6xx_bcms[] = { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + }, + { /* sentinel */ }, +}; + static const struct adreno_info a6xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x06010000), @@ -985,16 +996,7 @@ static const struct adreno_info a6xx_gpus[] = { .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020200, .prim_fifo_threshold = 0x00010000, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(3), - }, - { /* sentinel */ }, - }, + .bcms = a6xx_bcms, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, -- 2.56.0
