This adds Adreno 620 GPU found in Qualcomm SM7250 (Snapdragon 765/765G/768G) to msm driver. It is A650 derivative using a650 SQE/GMU firmware and a620_zap.mbn. On top of catalog entry it needs two A620 specific GMU changes:
- A620 has no PDC setup from AOP, so PDC sequencer is programmed from driver (xo/mx/cx addresses from cmd-db). Without it RSC never acks second power-up and device hangs. - A bandwidth table with BCM addresses of this SoC. The generic A630 one does not exist on SM7250, so first GX performance vote times out. Tested on OnePlus Nord (SM7250) running mainline: the GPU, GMU and Vulkan work. This needs the SM7250 SMMU series [1] as well, otherwise the device is reset when the first per-process pagetable is created. The SoC devicetree nodes are not part of this series; they will be sent separately once the SoC dtsi is accepted. [1] https://lore.kernel.org/all/[email protected]/ Signed-off-by: Ishu Brar <[email protected]> --- Changes in v2: - Patch 3: also program the VRM command (vrm.soc + 4) in TCS1 and TCS3 when cmd-db has it, as the downstream driver does (Konrad). - Patch 4: GMU clock gating mode is 0x00020202 as downstream (was 0x00020200); add the SH0/MC0/ACV BCM list for the generic bandwidth table. The bus widths are the ones the other A6xx/A7xx parts use. - Patch 2 is kept for now: the generic table is only used when the OPP table has bandwidth levels, which needs the SM7250 interconnect driver and DT that are not upstream yet. Without it the A620 would fall back to the A630 table. - Testing: v2 was re-tested on the OnePlus Nord (these changes on top of my 7.3-rc7 port tree, not on msm-next), with the interconnect path and OPP bandwidth levels in the GPU node. Vulkan workloads ran across GPU power cycles and all four GPU frequencies; each frequency selected its own bandwidth level, the generated BCM votes scale linearly with the OPP bandwidth and the GMU accepted the table. I could not read back the resulting DDR frequency. - Protect map (patch 4 follow-up suggested by Konrad): not included yet, waiting for the downstream reference of the 0x1c800 range. - Link to v1: https://patch.msgid.link/[email protected] To: Rob Clark <[email protected]> To: Dmitry Baryshkov <[email protected]> To: Abhinav Kumar <[email protected]> To: Jessica Zhang <[email protected]> To: Sean Paul <[email protected]> To: Marijn Suijten <[email protected]> To: David Airlie <[email protected]> To: Simona Vetter <[email protected]> To: Maarten Lankhorst <[email protected]> To: Maxime Ripard <[email protected]> To: Thomas Zimmermann <[email protected]> To: Rob Herring <[email protected]> To: Krzysztof Kozlowski <[email protected]> To: Conor Dooley <[email protected]> To: Konrad Dybcio <[email protected]> To: Akhil P Oommen <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] --- Ishu Brar (4): dt-bindings: display: msm: Document Adreno 620 and its GMU drm/msm/a6xx: Add a bandwidth table for the Adreno 620 GMU drm/msm/a6xx: Program the PDC sequencer on Adreno 620 drm/msm/adreno: Add Adreno 620 .../devicetree/bindings/display/msm/gmu.yaml | 2 ++ .../devicetree/bindings/display/msm/gpu.yaml | 1 + drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 35 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 35 ++++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 6 files changed, 106 insertions(+), 6 deletions(-) --- base-commit: d024361c631b3f020a26c07d683e5103404b0fbf change-id: 20261016-adreno-a620-faee699b382f Best regards, -- Ishu Brar <[email protected]>
