On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for > any output other than DP_A. However, the configuration register marks that > as being a test-only mode. Ok, it's all irrelevant -- the only configurations using anything other than a fixed 120MHz were eDP and LVDS. LVDS used a value from the BIOS, which is presumably always 120MHz. eDP ignored the refclk and used fixed PLL values. So, yes, we can always set the refclk to 120MHz; the cases which matter were using that value already. -- keith.packard at intel.com -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20110927/26719730/attachment.pgp>
