From: Maurice Hieronymus <[email protected]> The driver derives period and duty cycle from the clock rate read at probe, so a later rate change would silently miscompute waveforms. Switch to the new ExclusiveClk wrapper to hold the rate for the lifetime of the driver data and drop the corresponding TODO.
Reviewed-by: Alice Ryhl <[email protected]> Reviewed-by: Michal Wilczynski <[email protected]> Signed-off-by: Maurice Hieronymus <[email protected]> [ Adapted to ExclusiveClk<Enabled> and ExclusiveClk::new(), and rebased onto the vertical imports and DevresIoMem conversion. - Daniel ] Signed-off-by: Daniel Almeida <[email protected]> --- drivers/pwm/pwm_th1520.rs | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs index 5180b912efad..9be0a7f210b9 100644 --- a/drivers/pwm/pwm_th1520.rs +++ b/drivers/pwm/pwm_th1520.rs @@ -23,7 +23,8 @@ use kernel::{ clk::{ Clk, - Enabled, // + Enabled, + ExclusiveClk, // }, device::{ Bound, @@ -94,7 +95,7 @@ struct Th1520WfHw { struct Th1520PwmDriverData { #[pin] iomem: DevresIoMem<TH1520_PWM_REG_SIZE>, - clk: Clk<Enabled>, + clk: ExclusiveClk<Enabled>, } impl pwm::PwmOps for Th1520PwmDriverData { @@ -318,10 +319,8 @@ fn probe<'bound>( let request = pdev.io_request_by_index(0).ok_or(ENODEV)?; let clk = Clk::<Enabled>::get(dev, None)?; + let clk = ExclusiveClk::new(clk)?; - // TODO: Get exclusive ownership of the clock to prevent rate changes. - // The Rust equivalent of `clk_rate_exclusive_get()` is not yet available. - // This should be updated once it is implemented. let rate_hz = clk.rate().as_hz(); if rate_hz == 0 { dev_err!(dev, "Clock rate is zero\n"); -- 2.56.0
