On Tue, Sep 20, 2011 at 10:22 AM, Ilija Hadzic
<ihadzic at research.bell-labs.com> wrote:
> Enabling pcie gen2 speed was skipped for Northern Islands
> AISCs, although it looks like it works just fine with the same
> initialization sequence used for evergreen.
>
> According to Alex D. gen2 init was skipped to prevent a crash
> that has been caused by some other bug that has been
> fixed in the meantime; so now it should be safe to enable it.
>
> Signed-off-by: Ilija Hadzic <ihadzic at research.bell-labs.com>
I just double checked and BTC and cayman use the same programming
method. Both patches:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Thanks!
Alex
> ---
> ?drivers/gpu/drm/radeon/evergreen.c | ? ?3 +--
> ?1 files changed, 1 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen.c
> b/drivers/gpu/drm/radeon/evergreen.c
> index f09bace..208b59c 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -2987,8 +2987,7 @@ static int evergreen_startup(struct radeon_device *rdev)
> ? ? ? ?int r;
>
> ? ? ? ?/* enable pcie gen2 link */
> - ? ? ? if (!ASIC_IS_DCE5(rdev))
> - ? ? ? ? ? ? ? evergreen_pcie_gen2_enable(rdev);
> + ? ? ? evergreen_pcie_gen2_enable(rdev);
>
> ? ? ? ?if (ASIC_IS_DCE5(rdev)) {
> ? ? ? ? ? ? ? ?if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw ||
> !rdev->mc_fw) {
> --
> 1.7.6
>
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