Store the panel power sequencing delays in the dp private structure, rather than the global device structure. Who knows, maybe we'll get more than one eDP device in the future.
Look at both the current hardware register settings and the VBT specified panel power sequencing timings. Use the maximum of the two delays, to make sure things work reliably. If there is no VBT data, then those values will be initialized to zero, so we'll just use the values as programmed in the hardware. This patch computes power-up and power-down delays, rather than using portions of the appropriate delay values as found in the hardware. The eDP specified delay between raising VCC and communicating over the aux channel includes both the power rise time (T1) and the aux channel communication delay (T3). The eDP specified delay between powering down the device and powering it back up includes both the power fall time (T11) and the device idle time (T12).
