On 9/14/2026 5:33 AM, Dmitry Baryshkov wrote:
On Fri, Sep 11, 2026 at 09:06:40PM +0530, Nabige Aala wrote:
From: Ritesh Kumar <[email protected]>
Nord requires different AUX channel and VCO divider settings compared
to existing SoCs. Add edp_phy_aux_cfg_nord and edp_phy_vco_div_cfg_nord
with values sourced from HPG Tables 2-1-a and 2-1-b respectively.
Signed-off-by: Ritesh Kumar <[email protected]>
Signed-off-by: Nabige Aala <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c
b/drivers/phy/qualcomm/phy-qcom-edp.c
index 373f13b3d6d5..ee0d7f1a90fe 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -1508,6 +1508,25 @@ static int qcom_edp_phy_probe(struct platform_device
*pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+/*
+ * nord AUX config (eDP mode).
+ * From HPG Table 2-1-a: edp_phy_aux_bist.csv
+ * Index: 0 1 2 3 4 5 6 7 8 9 10 11
12
Drop useless comments.
Ack
+ */
+static const u8 edp_phy_aux_cfg_nord[DP_AUX_CFG_SIZE] = {
+ 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02,
0x04,
So, it's the same as edp_phy_aux_cfg_v5, except for the last register?
Yes, it is same as edp_phy_aux_cfg_v5 except for the last register.
you want to use the "edp_phy_aux_cfg_v5" for nord also?
+};
+
+/*
+ * nord VCO_DIV config for eDP mode.
+ * From HPG Table 2-1-b AUX Clock Settings (eDP mode) - Nominal/Turbo column.
+ * Indices: [0]=1620, [1]=2700, [2]=5400, [3]=8100
:-(
If it's AI, fix the AI prompt, please.
Sorry about that, that's on me. The AI-generated comments are a bit
excessive here. I will trim them down from all over the patch series.
Thanks,
Nabige
+ */
+static const u8 edp_phy_vco_div_cfg_nord[4] = {
+ 0x00, 0x00, 0x02, 0x01,
+};
+
+
static const struct of_device_id qcom_edp_phy_match_table[] = {
{ .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, },
{ .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
--
2.34.1
