On 9/14/2026 5:28 AM, Dmitry Baryshkov wrote:
On Fri, Sep 11, 2026 at 09:06:38PM +0530, Nabige Aala wrote:
From: Ritesh Kumar <[email protected]>
Nord relocates several DP PHY and QSERDES v8 COM registers relative
to existing SoCs. Add Nord-specific defines for the relocated and
new-only registers in phy-qcom-qmp-qserdes-dp-com-v8.h and
phy-qcom-edp.c so Nord sequences can reference them by name.
If the registers are reallocated it usually means that there are other
registers being inserted (or deleted). Are those the only registers
being changed?
Yes, only few register offset is changed that is taken care in this change.
Signed-off-by: Ritesh Kumar <[email protected]>
Signed-off-by: Nabige Aala <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 10 ++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c
b/drivers/phy/qualcomm/phy-qcom-edp.c
index a3c893f72908..bf8a17336c7e 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -41,9 +41,19 @@
#define DP_PHY_VCO_DIV 0x0074
#define DP_PHY_TX0_TX1_LANE_CTL 0x007c
+/* Nord uses a different register layout; non-Nord value is 0x00a0 */
#define DP_PHY_TX2_TX3_LANE_CTL 0x00a0
+#define DP_PHY_TX2_TX3_LANE_CTL_NORD 0x00c0
+/* Nord uses a different register layout; non-Nord value is 0x00e0 */
#define DP_PHY_STATUS 0x00e0
+#define DP_PHY_STATUS_NORD 0x0110
+#define DP_PHY_LDO_CFG 0x00f0
Why does it not have a _NORD suffix?
Ack, I will add _NORD suffix in the next revision.
Thanks
+
+/* Nord-specific TX lane registers */
+#define DP_PHY_TX_LN0_DRV_LVL_NORD 0x00e4
+#define DP_PHY_TX_LN1_DRV_LVL_NORD 0x00e8
+#define TXn_TX_BAND_NORD 0x0024
/* LANE_TXn registers */
#define TXn_CLKBUF_ENABLE 0x0000
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h
b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h
index 93edabb830af..008b17222a8d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h
@@ -48,5 +48,8 @@
#define DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4
#define DP_QSERDES_V8_COM_CMN_STATUS 0x314
#define DP_QSERDES_V8_COM_C_READY_STATUS 0x33c
+#define DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL_NORD 0x17c
+#define DP_QSERDES_V8_COM_CMN_STATUS_NORD 0x1d0
+#define DP_QSERDES_V8_COM_C_READY_STATUS_NORD 0x1f8
#endif
--
2.34.1
