On Thu, Sep 10, 2026 at 05:57:33PM +0100, Gary Guo wrote: > From: Gary Guo <[email protected]> > > `SectionFlags` and `MMU_MEMATTR_STAGE1` are not registers themselves. Use > `bitfield!` directly. > > Signed-off-by: Gary Guo <[email protected]> > --- > drivers/gpu/drm/tyr/fw.rs | 12 ++++-------- > drivers/gpu/drm/tyr/regs.rs | 11 +++++------ > 2 files changed, 9 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/tyr/fw.rs b/drivers/gpu/drm/tyr/fw.rs > index 7edb5eff1707..aea151ff1f93 100644 > --- a/drivers/gpu/drm/tyr/fw.rs > +++ b/drivers/gpu/drm/tyr/fw.rs > @@ -14,6 +14,7 @@ > //! [`Section`]: crate::fw::Section > > use kernel::{ > + bitfield, > device::{ > Bound, > Device, // > @@ -27,7 +28,6 @@ > }, > num::Bounded, > prelude::*, > - register, > str::CString, > sync::{ > Arc, > @@ -39,8 +39,7 @@ > use crate::{ > driver::{ > IoMem, > - TyrDrmDevice, > - TyrRegisters, // > + TyrDrmDevice, // > }, > fw::parser::{ > FwParser, > @@ -101,11 +100,8 @@ fn from(value: CacheMode) -> Self { > } > } > > -register! { > - base: TyrRegisters; > - > - #[allow(non_upper_case_globals)] > - pub(super) SectionFlags(u32) @ 0x0 { > +bitfield! { > + pub(super) struct SectionFlags(u32) { > 0:0 read => bool; > 1:1 write => bool; > 2:2 exec => bool; > diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs > index 0c419c4e1186..6f626957a010 100644 > --- a/drivers/gpu/drm/tyr/regs.rs > +++ b/drivers/gpu/drm/tyr/regs.rs > @@ -986,6 +986,7 @@ pub(crate) mod mmu_control { > /// This array contains 16 instances of the MMU_AS_CONTROL register page. > pub(crate) mod mmu_as_control { > use kernel::{ > + bitfield, > num::Bounded, > prelude::*, > register, // > @@ -1130,14 +1131,12 @@ fn from(val: MemoryType) -> Self { > } > } > > - register! { > - base: TyrRegisters; > - > + bitfield! { > /// Stage 1 memory attributes (8-bit bitfield). > /// > - /// This is not an actual register, but a bitfield definition > used by the MEMATTR > - /// register. Each of the 8 bytes in MEMATTR follows this layout. > - MMU_MEMATTR_STAGE1(u8) @ 0x0 { > + /// Each of the 8 bytes in MEMATTR follows this layout. > + #[allow(non_camel_case_types)] > + struct MMU_MEMATTR_STAGE1(u8) { > /// Inner cache write allocation policy. > 0:0 alloc_w => bool; > /// Inner cache read allocation policy.
Reviewed-by: Deborah Brouwer <[email protected]> > > base-commit: 73e5616f3d197c1af5a04a481fe0f13aa3913bd1 > -- > 2.54.0 >
